wu-arch/chipyard
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1399 Commits

Author SHA1 Message Date
Jerry Zhao
fba75e7a74 Bump constellation with improved TL-noc 2023-10-19 23:40:33 -07:00
Richard Yan
447eb24ec2 bump rocket-chip, testchipip 2023-10-19 17:12:33 -07:00
Hansung Kim
bfe7f1b9d7 Bump rocket-chip 2023-10-18 20:07:29 -07:00
Jerry Zhao
1d9dba517b Fix unassigned clocks due to removing implicit clock from BaseSubsystem 2023-10-18 18:59:22 -07:00
Jerry Zhao
646ba4fba7 Bump testchipip 2023-10-18 00:38:52 -07:00
Jerry Zhao
686d9a5f44 Bump rocket-chip 2023-10-18 00:27:05 -07:00
Jerry Zhao
e8aa68c65c Tiles do not generate interrupts 2023-10-17 17:05:45 -07:00
Jerry Zhao
5f51da3db3 Fix HasChipyardPRCI typos 2023-10-17 15:56:22 -07:00
Hansung Kim
1f7995c251 Bump rocket-gpu 2023-10-17 15:31:05 -07:00
Jerry Zhao
aa057239f2 Bump rocket-chip + submodules for new clustered-tile API 2023-10-17 14:38:28 -07:00
Hansung Kim
f71b0144ec Move args/op bin directory to sims/ 
This is to help ci find the binaries correctly for both vcs and verilator.
 2023-10-17 12:33:37 -07:00
Hansung Kim
27aad2b5ad Add generators/rocket-gpu submodule 2023-10-17 10:50:03 -07:00
Hansung Kim
e4c5aa5a0a Bump rocket-chip 2023-10-16 15:27:39 -07:00
Hansung Kim
3efeba3b4e Fix missing parameters for WithRadianceCores 2023-10-16 15:27:39 -07:00
Hansung Kim
632be3ad60 Bump rocket-chip 2023-10-16 01:22:14 -07:00
Jerry Zhao
6bd2e9dddb [ci skip] Re-add suggestName for axi4 mmio mem 2023-10-13 17:36:41 -07:00
Richard Yan
c965ee8cb5 bump rocket-chip and testchipip 2023-10-13 15:26:22 -07:00
Richard Yan
69d300d06f merge 2023-10-13 14:29:53 -07:00
Hansung Kim
355fedd79d Rename useVxCache 2023-10-13 14:23:24 -07:00
Richard Yan
246c1e81f0 Merge branch 'graphics' of https://github.com/hansungk/chipyard into graphics 2023-10-13 13:26:48 -07:00
Richard Yan
3a6c3c51b4 separate rom-based and non-rom-based configs; add bootrom to makefile 2023-10-13 13:26:46 -07:00
Jerry Zhao
deab3b11b6 Fix UARTAdapter div bits 2023-10-12 15:37:03 -07:00
Hansung Kim
304ea362d0 Bump rocket-chip 2023-10-11 20:32:51 -07:00
Jerry Zhao
3cbcf6b6e8 Fix TSIBridge loadmem param 2023-10-11 15:01:39 -07:00
Jerry Zhao
894ee63061 Make chipParameters not private 2023-10-11 14:59:49 -07:00
Jerry Zhao
8ecd7bfa89 Merge remote-tracking branch 'origin/main' into port_api 2023-10-09 11:18:00 -07:00
Hansung Kim
6198cc32b0 Bump rocket-chip 2023-10-07 02:31:35 -07:00
Jerry Zhao
8d11dde7cb Fix UARTPort freqMHz 2023-10-07 00:27:15 -07:00
Jerry Zhao
b949324d5a Fix FireSim UARTBridge 2023-10-06 17:55:14 -07:00
Jerry Zhao
a4cb114657 Fix UARTAdapter divisor 2023-10-06 17:00:06 -07:00
joonho hwangbo
a524adb1b9 Fix icenet-loopback clock and reset domain (#1612) 
* Fix

* Bump icenet

* revert icenet bump | fix harnessbinders
 2023-10-06 08:34:15 -07:00
Jerry Zhao
e6203bb25c Fix fsim supernode memmodel 2023-10-05 23:56:29 -07:00
Jerry Zhao
8fb4ba5675 Fix UARTPort freqMHz 2023-10-05 21:03:34 -07:00
Jerry Zhao
eb3a0aecf4 Add PortAPI between IO and Harness blocks 2023-10-05 15:02:56 -07:00
Hansung Kim
3d7caa41e8 Merge remote-tracking branch 'upstream/main' into graphics 
Bumped rocket-chip and testchipip to graphics
 2023-10-01 17:57:36 -07:00
joshua
12e66e76c5 bump rocket + update VortexCache config 2023-09-29 00:54:55 -07:00
joshua
0de6ec7c0f Merge remote-tracking branch 'origin/graphics' into graphics 2023-09-28 11:39:03 -07:00
-T.K.-
8fa8be5669 ADD: bump testchipip 2023-09-27 10:54:57 -07:00
Richard Yan
50277f3209 bump rocket-chip and testchipip 2023-09-27 10:54:26 -07:00
Jerry Zhao
adebd634b4 Fix Arty100T Verilog build (#1608) 
* Bump rocket-chip
* Bump fpga-shells
* Add Arty100T Verilog build to CI
* Fix Arty100T harness disconnected LEDs
 2023-09-27 13:03:37 +02:00
Richard Yan
ec63986310 fix testchipip 2023-09-26 16:16:05 -07:00
joshua
52c79e4b15 Merge remote-tracking branch 'origin/graphics' into graphics 2023-09-25 23:44:23 -07:00
joshua
477e88f95b new rocketconfig for vx_cache 2023-09-25 23:44:12 -07:00
Richard Yan
8a2aa54a1c add operand roms, point testchipip to fork, bump rocket 2023-09-25 21:29:25 -07:00
-T.K.-
f3c7ecf8ba REFACTOR: change bootaddr and reset vector address 2023-09-23 19:17:54 -07:00
Jerry Zhao
8c3a586c73 Add NarrowRocketCache config fragment 
For configs with wide SBUS, a narrow rocket cache is easier to PD, and does not incur any performance loss usually
 2023-09-20 15:53:13 -07:00
Jerry Zhao
7106200d9d Fix HarnessClockInstantiatorEx doc reference 2023-09-20 11:46:42 -07:00
Jerry Zhao
9ab5067e35 Update docs on bringup sims 2023-09-20 11:44:43 -07:00
Jerry Zhao
57ee757016 Remove MultiClockHarnessAXIMem 
Previously, the MultiClockHarnessAXIMem stuff attached SimDRAM over the serial-tl link.
This was done to enable test-chip-like simulations, where the HarnessBinder/BridgeBinder
would effectively implement a similar system as what would go on the bringup platform.

Now that multi-chip-tops are supported, and co-simulation of the ChipTop and the BringupTop
are supported, we can remove all this old Harness-level stuff to reduce duplication
 2023-09-16 09:47:47 -07:00
Richard Yan
1c76515f17 add args.bin and large extmem to config 2023-09-15 11:18:22 -07:00