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separate rom-based and non-rom-based configs; add bootrom to makefile

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This commit is contained in:
Richard Yan
2023-10-13 13:26:46 -07:00
parent 50277f3209
commit 3a6c3c51b4
2 changed files with 12 additions and 7 deletions
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17
generators/chipyard/src/main/scala/config/RocketConfigs.scala
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@@ -35,17 +35,22 @@ class WithRadBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigIn
))
})
class RadianceROMConfig extends Config(
new freechips.rocketchip.subsystem.WithRadianceCores() ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new WithExtMemSize(BigInt("80000000", 16)) ++
new WithRadBootROM() ++
new WithRadROMs(0x7FFF0000L, 0x10000, "sims/vcs/args.bin") ++
new WithRadROMs(0x20000L, 0x8000, "sims/vcs/op_a.bin") ++
new WithRadROMs(0x28000L, 0x8000, "sims/vcs/op_b.bin") ++
new AbstractConfig)
class RadianceConfig extends Config(
new freechips.rocketchip.subsystem.WithRadianceCores() ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
// new freechips.rocketchip.subsystem.WithNoMemPort ++
// new testchipip.WithSbusScratchpad(banks=2) ++
// new testchipip.WithMbusScratchpad(banks=2) ++
new WithExtMemSize(BigInt("80000000", 16)) ++
new WithRadBootROM() ++
new WithRadROMs(0x7FFF0000L, 0x10000, "sims/vcs/args.bin") ++
new WithRadROMs(0x20000L, 0x8000, "sims/vcs/op_a.bin") ++
new WithRadROMs(0x28000L, 0x8000, "sims/vcs/op_b.bin") ++
new testchipip.WithMbusScratchpad(base=0x7FFF0000L, size=0x10000, banks=1) ++
new AbstractConfig)
class TinyRocketConfig extends Config(