Jerry Zhao
bf010668e3
Bump firechip
2024-01-26 18:40:08 -08:00
Jerry Zhao
835562238a
Explicitly pass chipId to all HarnessBinders
2023-12-26 18:37:39 -08:00
Jerry Zhao
194d4462f9
Update testchipip with source-synchronous serdes
2023-12-21 20:33:24 -08:00
Jerry Zhao
cfd555ee94
Bump testchipip for updated sertl type names
2023-12-21 14:18:06 -08:00
Jerry Zhao
1e5ebf192a
Update firesim/firechip with new testchipip packaging
2023-12-19 12:11:12 -08:00
Jerry Zhao
d83f395738
Update firechip for new testchipip
2023-10-24 18:42:27 -07:00
Jerry Zhao
3cbcf6b6e8
Fix TSIBridge loadmem param
2023-10-11 15:01:39 -07:00
Jerry Zhao
b949324d5a
Fix FireSim UARTBridge
2023-10-06 17:55:14 -07:00
Jerry Zhao
eb3a0aecf4
Add PortAPI between IO and Harness blocks
2023-10-05 15:02:56 -07:00
Jerry Zhao
57ee757016
Remove MultiClockHarnessAXIMem
...
Previously, the MultiClockHarnessAXIMem stuff attached SimDRAM over the serial-tl link.
This was done to enable test-chip-like simulations, where the HarnessBinder/BridgeBinder
would effectively implement a similar system as what would go on the bringup platform.
Now that multi-chip-tops are supported, and co-simulation of the ChipTop and the BringupTop
are supported, we can remove all this old Harness-level stuff to reduce duplication
2023-09-16 09:47:47 -07:00
abejgonzalez
a48746f113
Deprecate Dromajo in FireSim, use cospike
...
Move Cospike to testchipip
2023-08-30 17:55:04 -07:00
Jerry Zhao
b69bcffc91
Merge remote-tracking branch 'origin/main' into unify
2023-05-19 11:28:52 -07:00
Jerry Zhao
d4d81f7d22
Rename serialManagerParams -> serialTLManagerParams
2023-05-13 19:25:14 -07:00
Jerry Zhao
3330c23193
Support uni-directional TLSerdesser
2023-05-13 14:14:38 -07:00
Jerry Zhao
607c2b5a73
Unify multi-node btw chipyard/firechip | unify harness clocking
2023-05-12 08:41:34 -07:00
Jerry Zhao
eced8e63d9
Rename SerialAdapter+SimSerial to TSIToTileLink/SimTSI/TSIHarness
2023-05-08 18:19:18 -07:00
Jerry Zhao
ac281daa78
Move TestHarness to chipyard.harness, make chipyard/harness directory
2023-05-08 08:00:56 -07:00
Jerry Zhao
4f5bbdca97
Flip serial_tl.clock for firechip BridgeBinders
2023-05-07 22:22:37 -07:00
Jerry Zhao
df2e5ad9dc
Bump to latest rocket-chip/chisel3.5.6
2023-03-28 16:48:27 -07:00
abejgonzalez
a62c1f5010
Add a frag./config for MMIO only bridges
2023-03-09 20:09:46 -08:00
Jerry Zhao
7780ed23bf
Bump to scala 2.13.10/chisel 3.5.5/latest rocketchip
2023-01-26 00:12:28 -08:00
abejgonzalez
09ef82cabf
Update harnessClk/Rst naming to buildtop | Small docs cleanup
2021-03-22 13:11:12 -07:00
abejgonzalez
5ffad327db
Bump testchipip
2021-03-21 15:34:01 -07:00
abejgonzalez
55263971bc
Use async queue to connect serdesser + other components
2021-03-19 20:49:49 -07:00
abejgonzalez
6476c7e7f0
Small renaming/cleanup | Use LinkedHashMaps
2021-03-15 16:54:42 -07:00
Jerry Zhao
a013f0d561
Fix SerialTL HarnessRAM BridgeBinder
2021-03-15 15:09:29 -07:00
Jerry Zhao
8a78565c04
Update BridgeBinders with new HarnessRAM clocking
2021-03-15 12:45:40 -07:00
Abraham Gonzalez
6ab8f8f8fc
Update FireSim to support harness clocks | Small config renaming
2021-03-08 22:03:07 +00:00
Abraham Gonzalez
c52fce79ae
Fix FireChip compilation | Remove extra DefaultSerialTL in bridges
2021-03-03 07:25:49 +00:00
abejgonzalez
f850df7a9f
General renaming / cleanup
2021-03-02 22:58:05 -08:00
Abraham Gonzalez
1d287bede5
Enlarge serial width | Bugfix loadmem disable | Add TracerV
2021-03-03 02:43:38 +00:00
Abraham Gonzalez
a3e22c78de
First attempt at getting Offchip AXI port
2021-02-28 22:27:18 +00:00
alonamid
6dcd4f9afc
WithFireSimFAME5 to allow non Rocket/BOOM build
2021-02-01 17:33:07 -08:00
David Biancolin
ee436c9b3f
[firechip] Fix a uart multiclock bug
2020-12-10 07:18:12 +00:00
abejgonzalez
a2ebbee2ac
Rename Ariane to CVA6
2020-11-04 15:42:30 -08:00
Jerry Zhao
e0bf907a06
Merge remote-tracking branch 'origin/dev' into lazy-iobinders
2020-10-19 13:22:01 -07:00
Jerry Zhao
9927231bc4
Support lazy-iobinders
2020-10-17 22:47:50 -07:00
Albert Magyar
84e0bf7338
Don't annotate cores with FAMEModelAnnotations
2020-10-15 12:25:39 -07:00
David Biancolin
6aefb73ab5
Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-mbus-crossing
2020-10-14 15:29:00 -07:00
David Biancolin
986b5831c8
[clocking] Sketch out a topology that puts the MBUS is a separate domain
2020-10-09 07:23:17 -07:00
Jerry Zhao
b057cfbd8c
Merge remote-tracking branch 'origin/dev' into clocking-features
2020-10-01 20:12:20 -07:00
Jerry Zhao
79042e4ce8
Bump to support firesim simulation of no-AXI4DRAM designs
2020-10-01 10:21:43 -07:00
Albert Magyar
2f5790d611
Add model multi-threading annotations (ignored by default) to FireChip
2020-09-30 23:32:49 -07:00
David Biancolin
b76972d34b
Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-pll-redux
2020-09-25 11:02:51 -07:00
David Biancolin
7b8a954d04
[firechip] Rework FireSim clocking to be more similar to default CY targets
2020-09-24 23:32:07 -07:00
Jerry Zhao
0d8e87126c
Deprecate support for on-chip SerialAdapter
2020-09-14 19:43:32 -07:00
Jerry Zhao
f9cc1dc2c2
Merge remote-tracking branch 'origin/dev' into serial-tl
2020-09-14 19:35:43 -07:00
Jerry Zhao
10625a3a6c
Undo regression in iocells flexibility
2020-09-14 13:27:31 -07:00
Jerry Zhao
6c5bce5430
Support Tilelink over serial
2020-09-13 11:59:16 -07:00
Jerry Zhao
a5385c0a54
Update testchipip/icenet to use rocket-chip Located API
2020-09-11 00:02:07 -07:00
