Abraham Gonzalez
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56b5cea816
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Merge branch 'dev' into filter-c-files
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2019-07-17 15:20:51 -07:00 |
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abejgonzalez
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5cedeea352
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model verilator args after vcs make
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2019-07-17 11:45:32 -07:00 |
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abejgonzalez
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b7bc96b6d6
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rename missing vcs/verilator names | fix ci path
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2019-07-16 21:36:36 -07:00 |
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abejgonzalez
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b0b4078801
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rename files | only remove .h on blackbox files
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2019-07-16 18:55:44 -07:00 |
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abejgonzalez
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27641bdffc
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Merge remote-tracking branch 'origin/dev' into filter-c-files
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2019-07-16 16:56:58 -07:00 |
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Abraham Gonzalez
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d5f9f1e94e
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Make verilator wget safe
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2019-07-16 15:26:44 -07:00 |
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abejgonzalez
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85d904f108
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add blkdev ci | cleanup simfiles to remove duplicates
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2019-07-16 11:34:26 -07:00 |
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abejgonzalez
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01f21900fe
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Merge remote-tracking branch 'origin/dev' into cleanup
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2019-07-16 10:43:28 -07:00 |
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Colin Schmidt
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26a67fdbad
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Add verbose to debug runs (#148)
* Add verbose to debug runs
* Reorg simulator flags for consistency, extensibility, and ease of use
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2019-07-15 22:15:57 -07:00 |
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abejgonzalez
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fd5a00a0ab
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rename sim dirs | add "fast" helper target | re-add -q flag
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2019-07-15 16:51:17 -07:00 |
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abejgonzalez
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5337a4472d
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cleaner implementation of dedup
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2019-07-11 09:52:06 -07:00 |
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abejgonzalez
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228cd36301
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remove duplicate blackbox files | general grep
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2019-07-10 13:35:19 -07:00 |
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abejgonzalez
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87e4090e38
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bump boom | correct error on first cmd in pipe
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2019-07-08 14:31:41 -07:00 |
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abejgonzalez
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ef1620b753
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update verilator.mk to support different install location
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2019-07-06 15:13:37 -07:00 |
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David Biancolin
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473bc0aa4e
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Comment out FireChip make variables for now
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2019-06-28 23:54:08 +00:00 |
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David Biancolin
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1f48e33be5
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Bump FireSim, and add back the firrtl intrp lib dep
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2019-06-28 19:16:34 +00:00 |
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David Biancolin
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f65d5d57d6
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Bump FireSim
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2019-06-28 19:01:44 +00:00 |
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David Biancolin
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1bd9b08717
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Merge branch 'rebar-dev' of https://github.com/ucb-bar/project-template into firesim-integration
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2019-06-28 18:10:19 +00:00 |
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abejgonzalez
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4cca0ed57e
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bump verilator version
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2019-06-19 09:35:46 -07:00 |
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David Biancolin
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d9a82e914c
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Bump FireSim
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2019-05-29 22:29:24 +00:00 |
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David Biancolin
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0cb1608e2c
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Bump FireSim
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2019-05-29 15:34:56 +00:00 |
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David Biancolin
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baf7a6c30d
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Bump FireSim
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2019-05-29 00:50:40 +00:00 |
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David Biancolin
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c0d4e848ba
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WIP
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2019-05-27 22:53:05 +00:00 |
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abejgonzalez
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cc0d33ee4d
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updated permissive naming | small bugfix for vcd/vpd dumping
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2019-05-20 17:19:46 -07:00 |
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abejgonzalez
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30d54a6851
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readme addition | pipe out output | renamed output files
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2019-05-20 17:12:22 -07:00 |
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abejgonzalez
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65d6a900c3
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rename output | helper rules to run binaries
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2019-05-20 16:15:08 -07:00 |
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Jerry Zhao
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340ed90652
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Remove permissive flag for verisim
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2019-05-11 19:59:49 -07:00 |
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Jerry Zhao
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ca3678087c
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Add verilator_install make target for CI purposes
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2019-05-10 17:06:03 -07:00 |
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Jerry Zhao
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cf9ef97676
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Fix verilator clean
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2019-05-07 23:05:13 -07:00 |
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Jerry Zhao
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2f2243df40
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Minor Makefile fixes
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2019-05-07 21:56:50 -07:00 |
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Jerry Zhao
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b88937b8a0
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Fix vcs tests for rocketchip and hwacha
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2019-04-24 18:23:26 -07:00 |
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abejgonzalez
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4c3dc0889c
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update make variable names | change hwacha to use its own generator
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2019-04-24 00:43:44 -07:00 |
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abejgonzalez
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2bd70937cb
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support verilator | rename build variable
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2019-04-22 23:26:13 -07:00 |
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abejgonzalez
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e4aa81b2f8
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fix make clean
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2019-04-18 14:25:37 -07:00 |
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abejgonzalez
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7d887b212c
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align rebar with tip of project-template master | fixes build issues
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2019-04-17 16:02:44 -07:00 |
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abejgonzalez
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c364869563
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default to .gitignoring all files in verisim/vsim | read verilator.mk
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2019-03-12 14:39:15 -07:00 |
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abejgonzalez
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2c246af110
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rename makefiles | move verilog rule to common.mk
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2019-03-12 14:39:15 -07:00 |
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abejgonzalez
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82273107c1
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makefile changes/split | add scripts
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2019-03-12 14:39:15 -07:00 |
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alonamid
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2def0dfea7
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change dir structure
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2019-03-12 14:30:38 -07:00 |
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