Commit Graph

8 Commits

Author SHA1 Message Date
Jerry Zhao
06b16e865e Move boom's tracegen interface to boom submodule - this improves maintainability 2023-02-08 09:35:13 -08:00
Jerry Zhao
578ae6fca2 Bump to July 2020 rocketchip 2020-08-04 14:00:02 -07:00
Jerry Zhao
a1cc62b85a Bump Rocket-chip again 2020-06-20 12:28:03 -07:00
Jerry Zhao
d245df9133 Bump Rocketchip to June 2020 for Tile changes 2020-06-18 17:25:31 -07:00
Colin Schmidt
43f6083b69 Many changes to begin the compilation with RC-1.3
Cores now have an extra CoreParam, useSupervisor which was set to
the default false. Whether a core has supervisor mode is the union
of this and useVM which defaults true so not change was made by this
addition.

BusTopologies are now set with the Config system rather than a system
mixin and so all configs now include the config most similar to the
previous mixin
Testchipip was updated to be able to replace the systembus, in this
new config system, with a ring bus.

The L2 cache repo needed a similar update on how to find the buses.
It currently points to the ucb-bar fork

Treadle is bumped to its release branch
2020-05-05 15:14:24 -07:00
David Biancolin
b303cf6e81 Rocket Chip Stage/Phase Bump (#503)
[WIP] Minimally elaborating design

Bring up a feature-complete Chipyard stage

Pull in Makefrag generation; Bump submodules

Update config generation, and global reset scheme

Bump submodules; clean up

Bump FireSim

Remove some unhygenic comments / WS

Remove the rocketchip subproject

[CI] Lengthen ariane tests timeout

Address some remaining reviewer comments

[firechip] Refresh a Field that cannot be used across repeated instantiations

Bump all submodules
2020-04-18 17:54:27 +00:00
Jerry Zhao
05f17f5b99 [tracegen] Add tracegen support for the BOOM L1D (#362)
* [tracegen] Add tracegen support for the BOOM L1D

* [tracegen] Split up BOOM Tracegen mixin and shim.

* [ci] Fix tracegen hash for testing
2020-01-23 16:01:32 -08:00
Howard Mao
6a3212c6d7 add tracegen project 2019-08-30 11:38:07 -07:00