wu-arch/chipyard
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Author SHA1 Message Date
Jerry Zhao
578ae6fca2 Bump to July 2020 rocketchip 2020-08-04 14:00:02 -07:00
Jerry Zhao
fdfef878af Merge branch 'dev' into diplomatic-clocks 2020-07-21 11:21:51 -07:00
Fang, Zitao
11c1e87638 Merge pull request #615 from ucb-bar/custom-core-doc 
Documentation for Third-Party Core Integration
 2020-07-20 11:56:56 -07:00
Zitao Fang
692b120b65 Fixed typo 2020-07-19 21:48:07 -07:00
Zitao Fang
0a39819f44 Add source file note 2020-07-19 21:46:32 -07:00
Zitao Fang
2c7e7f3199 Fixed file links 2020-07-19 21:36:50 -07:00
Zitao Fang
fddf218147 5th revision 2020-07-16 15:39:07 -07:00
Jerry Zhao
862d1fb774 Merge pull request #627 from ucb-bar/firrtl-logging 
Add variable to control FIRRTL logging verbosity
 2020-07-16 13:45:57 -07:00
Zitao Fang
97b8c3035c Merge branch 'dev' of github.com:ucb-bar/chipyard into custom-core-doc 2020-07-15 11:15:46 -07:00
Zitao Fang
9fbc0a5bea Add links 2020-07-15 11:08:36 -07:00
Zitao Fang
7ea464dc90 4th revision 2020-07-14 12:49:36 -07:00
Zitao Fang
14399e88b3 Minor change 2020-07-12 01:23:34 -07:00
Zitao Fang
ced7ea634c 3rd Revision 2020-07-12 01:08:13 -07:00
David Biancolin
d5a2d43f85 Merge pull request #612 from ucb-bar/zynq-target 
[firechip] Add a small target that should fit on all hosts
 2020-07-10 18:12:34 -07:00
Albert Ou
fbc71d4215 Merge pull request #625 from ucb-bar/uart 
Override default baud rate for FireChip
 2020-07-10 10:55:50 -07:00
Jerry Zhao
f8c9b316e2 Merge pull request #620 from ucb-bar/simple_configs 
Deduplicate across Chipyard configs into a ChipyardBaseConfig
 2020-07-09 17:12:19 -07:00
Jerry Zhao
2196a621c6 Pass FIRRTL_LOGLEVEL to GenerateTopAndHarness 2020-07-09 12:39:17 -07:00
Jerry Zhao
8124ce3df1 Add FIRRTL_LOGLEVEL variable 2020-07-09 12:38:21 -07:00
Jerry Zhao
7239e23185 Merge branch 'dev' into simple_configs 2020-07-09 11:31:33 -07:00
Jerry Zhao
11c87777fe Remove BOOM debug print 2020-07-09 11:29:58 -07:00
Albert Ou
84620e027b Merge pull request #626 from ucb-bar/testchipip 
Bump testchipip for bug fixes
 2020-07-08 23:01:35 -07:00
Zitao Fang
9ad9d00a23 Second revision 2020-07-08 16:02:31 -07:00
Albert Ou
763ba42b4c Bump testchipip for FDT alignment and minLatency fixes 2020-07-08 12:36:09 -07:00
Albert Ou
b55e579c91 Override default baud rate for FireChip 
This avoids target software needing to explicitly set the divisor to
match the UART bridge.
 2020-07-07 23:00:14 -07:00
Jerry Zhao
56e1aeb400 Support FireSim diplomatic multiclock 2020-07-07 20:54:31 -07:00
Fang, Zitao
60f7ec60bd Merge pull request #588 from ucb-bar/ariane-decouple 
Test Suite Simplification
 2020-07-07 12:55:52 -07:00
Jerry Zhao
c023cf0688 Rough initial implementation of diplomatic multiclock 2020-07-06 22:01:26 -07:00
Jerry Zhao
661038f992 Deduplicate across Chiypard configs into a ChipyardBaseConfig 2020-07-06 17:54:24 -07:00
Zitao Fang
6cb8a60a80 Remove Key List 2020-07-05 21:18:31 -07:00
Zitao Fang
744e73fa92 Editing Docs 2020-07-05 21:05:21 -07:00
Jerry Zhao
d3721bbd99 Merge pull request #618 from ucb-bar/mmio_fix 
Fixes for AXI4 MMIO and FBus ports
 2020-07-03 12:15:50 -07:00
Jerry Zhao
a7047c4ba2 Fix FireChip BridgeBinders 2020-07-03 08:33:10 -07:00
Zitao Fang
104c350a59 Custom Core Integration Doc, 1st Revision 2020-07-02 15:56:15 -07:00
Jerry Zhao
863f723708 Pipe through AXI4 MMIO and Slave ports to ChipTop | IOBinders fix 
* Fixes bug with AXI4 MMIO ports not being generated properly due to
   IOBinders issue. Additionally adds IOCells to AXI4 ports so that they
   appear in ChipTop
 * Change IOBinders to also require passing p: Parameters
   to child functions. Serialization of type targets via ClassTags fails
   for compound types, so we cannot use `BaseSubsystem with HasSomeTrait`
   as the type target in OverrideIOBinders.
 2020-06-30 13:42:06 -07:00
Zitao Fang
d77c4afb36 Rollback .gitignore 2020-06-29 12:05:24 -07:00
Zitao Fang
c85d8c4211 Remove generic parameter from this PR 2020-06-29 11:42:34 -07:00
Zitao Fang
d9556e14f5 Merge branch 'dev' of github.com:ucb-bar/chipyard into ariane-decouple 2020-06-28 21:39:32 -07:00
Zitao Fang
7b5f474b04 Finished Custom Core Docs 2020-06-28 21:26:50 -07:00
Zitao Fang
42f93ff32d Merge branch 'dev' of github.com:ucb-bar/chipyard into custom-core-doc 2020-06-28 21:26:09 -07:00
David Biancolin
1dd3ea4aeb Update TargetConfigs.scala 2020-06-27 13:44:52 -07:00
David Biancolin
863e68ff30 Merge pull request #576 from ucb-bar/make-suffix-rules 
Disable all make suffix rules for improved EC2 performance
 2020-06-27 13:37:16 -07:00
David Biancolin
aad28dccdb Merge pull request #613 from ucb-bar/bloop 
Bloop Support
 2020-06-27 13:36:52 -07:00
David Biancolin
02c889b8b1 Bump FireSim 2020-06-25 17:42:38 -07:00
David Biancolin
fe5785a3d6 Merge remote-tracking branch 'origin/dev' into bloop 2020-06-25 15:32:24 -07:00
David Biancolin
a0f103e843 [make] Specify a custom bloop server port w/ BLOOP_NAILGUN_PORT 2020-06-25 14:14:08 -07:00
Zitao Fang
1c5bc7d0ff Integrate with new Rocket tile API 2020-06-24 20:55:37 -07:00
Zitao Fang
df90442088 Merge branch 'dev' of github.com:ucb-bar/chipyard into ariane-decouple 2020-06-24 16:44:07 -07:00
Jerry Zhao
84e672cabb Merge pull request #605 from ucb-bar/rc-retile 
Bump Rocketchip to June 2020 for Tile changes
 2020-06-24 14:19:05 -07:00
Jerry Zhao
ec8089eff1 Merge remote-tracking branch 'origin/dev' into rc-retile 2020-06-23 17:00:01 +00:00
Jerry Zhao
16c8f47202 Bump Firesim 2020-06-23 16:31:41 +00:00