Jerry Zhao
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d51a9a74d3
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Merge remote-tracking branch 'origin/main' into clusters
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2024-01-09 13:30:26 -08:00 |
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Jerry Zhao
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604cb6358f
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Bump fpga-platforms to new organized testchipip
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2023-12-19 12:33:37 -08:00 |
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Jerry Zhao
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b02621db35
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Merge remote-tracking branch 'origin/main' into clusters
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2023-12-16 17:00:34 -08:00 |
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Jerry Zhao
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e7f10348b0
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Merge remote-tracking branch 'origin/main' into clusters
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2023-12-15 16:46:51 -08:00 |
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Jerry Zhao
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30ac9dc2c8
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Merge remote-tracking branch 'origin/main' into tcip-bump
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2023-12-14 10:58:57 -08:00 |
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Jerry Zhao
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a8766ea8fc
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Precisely specify bus frequencies
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2023-10-31 14:25:16 -07:00 |
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Jerry Zhao
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3fa3d745b9
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Support breaking out ChipTop I/O out of the expected bundle type
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2023-10-30 21:25:11 -07:00 |
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Jerry Zhao
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a5597fd32f
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Support using HarnessBinders without IOBinders
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2023-10-25 11:49:16 -07:00 |
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Jerry Zhao
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b4d4e54f9c
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Bump fpga-shells
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2023-10-24 18:24:44 -07:00 |
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Jerry Zhao
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1e26618e8d
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Fix fpga platforms cbus freq
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2023-10-21 15:48:01 -07:00 |
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Jerry Zhao
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eb3a0aecf4
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Add PortAPI between IO and Harness blocks
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2023-10-05 15:02:56 -07:00 |
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Jerry Zhao
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0b81a82459
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Fix VCU118 freq adjustment configs
Resolves #1583
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2023-09-06 10:55:53 -07:00 |
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Jerry Zhao
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078bce1323
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Bump to chisel3.6
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2023-07-05 10:32:55 -07:00 |
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jerryho
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9844deb172
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using dp(ExtTLMem).get.master.beatBytes to obtain MemoryBus data width
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2023-05-27 18:12:56 +08:00 |
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jerryho
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45eeee5092
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fix the data field width mismatch between AXI that goes to MIG core and that of the Memory Bus
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2023-05-26 16:08:59 +08:00 |
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Jerry Zhao
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57f5168408
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Set number of idbits correctly for fpga ddr
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2023-05-15 00:04:12 -07:00 |
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Jerry Zhao
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f4739be632
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Update multi-chip API for harnesses
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2023-05-15 00:03:22 -07:00 |
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Jerry Zhao
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2077e4304d
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Explicitly provide refClockFreqMHz to harnessClockInstantiator
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2023-05-13 11:18:03 -07:00 |
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Jerry Zhao
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b8e95e0305
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Rename implicit clock/reset to referenceclock/reset
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2023-05-12 15:11:44 -07:00 |
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Jerry Zhao
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607c2b5a73
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Unify multi-node btw chipyard/firechip | unify harness clocking
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2023-05-12 08:41:34 -07:00 |
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Jerry Zhao
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64ad77bbcf
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Make FPGA flows use the harnessClockInstantiator
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2023-05-11 15:04:04 -07:00 |
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Jerry Zhao
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ac281daa78
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Move TestHarness to chipyard.harness, make chipyard/harness directory
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2023-05-08 08:00:56 -07:00 |
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Jerry Zhao
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df2e5ad9dc
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Bump to latest rocket-chip/chisel3.5.6
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2023-03-28 16:48:27 -07:00 |
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Jerry Zhao
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85fa9d1120
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Add ARTY100t bringup + TSI-over-UART
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2023-02-14 15:01:52 -08:00 |
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abejgonzalez
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292cc753ce
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Run pre-commit on all files
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2022-12-21 15:59:46 -08:00 |
|
Lori Li
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0724431873
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Clean up code
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2022-11-30 16:56:09 +09:00 |
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Jerry Zhao
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f668ffdb03
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Switch PRCI to HarnessBinder/IOBinders
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2021-09-29 11:39:52 -07:00 |
|
Abraham Gonzalez
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985faa4c8e
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Small comment updates + cleanup
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2021-04-03 12:55:27 -07:00 |
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Abraham Gonzalez
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be13781a1c
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Set both MBUS/PBUS in configs | Add simple check for correct clocks
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2021-04-02 16:43:59 -07:00 |
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Abraham Gonzalez
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5a41c5d9ac
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Use multi-clock config. frags to determine VCU118 clk freq
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2021-04-01 16:21:44 -07:00 |
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abejgonzalez
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09ef82cabf
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Update harnessClk/Rst naming to buildtop | Small docs cleanup
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2021-03-22 13:11:12 -07:00 |
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abejgonzalez
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9957538d38
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Enable support for pullup R's on GPIOs
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2021-02-25 13:54:53 -08:00 |
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abejgonzalez
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4d3ff26a73
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Bump testchipip
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2021-01-04 15:36:00 -08:00 |
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abejgonzalez
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f1fdab5bd3
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Move TL mem switch frag to CY | Add require to not have TL/AXI backing mem
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2020-11-23 16:58:34 -08:00 |
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abejgonzalez
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8f6de22e72
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Fixed TinyRocketConfig | Small cleanup to VCU118/Arty configs
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2020-11-23 16:30:39 -08:00 |
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abejgonzalez
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661a7701a7
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Share DigitalTop/ChipyardSystem | Fix small naming compile error
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2020-11-23 15:46:03 -08:00 |
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abejgonzalez
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d94a8efd43
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Fix TLMemPort comment | Use Option instead of NoSimulator
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2020-11-15 15:44:38 -08:00 |
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abejgonzalez
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c8add488ad
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Reduce BOOM default freq. (play it safe)
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2020-11-15 14:31:14 -08:00 |
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abejgonzalez
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55f19f79d3
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Address fpga srcs
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2020-11-12 15:39:29 -08:00 |
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abejgonzalez
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7ca3be236c
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Bump bringup VCU118 | Ignore HTIF if no-debug module
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2020-11-12 11:47:16 -08:00 |
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abejgonzalez
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082b230452
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Add missing file
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2020-11-08 17:51:21 -08:00 |
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abejgonzalez
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244205e2b4
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Separate new sys_clk and ddr2 from TSI
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2020-11-08 17:49:32 -08:00 |
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Abraham Gonzalez
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5a4cad0172
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Merge pull request #6 from ucb-bar/local-fpga-support-docs
Local fpga support docs
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2020-11-06 21:03:15 -08:00 |
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abejgonzalez
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c5e8fecb5c
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Small renaming and cleanup
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2020-11-06 21:00:18 -08:00 |
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Abraham Gonzalez
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9144e3c706
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Fix pin mappings for TSI DDR
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2020-11-06 20:51:11 -08:00 |
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abejgonzalez
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7baa1341ee
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Use 2nd system clock for TSI DDR | Small cleanups
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2020-11-06 16:34:45 -08:00 |
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abejgonzalez
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6aae66c54f
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Add TSI Host Widget
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2020-11-06 15:50:28 -08:00 |
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Abraham Gonzalez
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b0eed5075f
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[temp] start integrating tsi host widget
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2020-11-06 10:57:55 -08:00 |
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abejgonzalez
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84508bee6e
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More FPGA prototyping docs
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2020-11-05 21:51:25 -08:00 |
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abejgonzalez
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313fa4f129
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Merge branch 'local-fpga-support' into local-fpga-support-docs
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2020-11-05 21:24:03 -08:00 |
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