Abraham Gonzalez
be3b05a909
add test case
2019-10-28 13:45:05 -07:00
Colin Schmidt
c23b2b6f84
SRAM depth to bigint
...
max synflop depth support
Fix annotation mangling on the harness side
2019-05-14 10:10:47 -07:00
Colin Schmidt
affd033f0a
Emit hammer IR from MacroCompiler ( #50 )
2019-03-25 22:52:39 -07:00
Colin Schmidt
0b9d74ada7
Fix unit tests update cost function once more
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bump mdf to master
2019-03-18 07:25:04 -07:00
edwardcwang
93bf7895be
Fix corner case in compiling a small mem using a large lib ( #32 )
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* Refactor bit pairs calculation into a separate function
* Minor clarifications
* Clarify MacroCompilerSpec helpers
* Add SmallTagArrayTest test
* Fix corner case in compiling a small mem using a large lib
2018-04-26 10:33:55 -07:00
Adam Izraelevitz
79c8c283cc
Add memory compiler to macros ( #29 )
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* Add memory compiler to macros
* Removed weird spacing
* Make sramcompiler width/depth range inclusive
* Added sramcompiler test
2018-02-16 16:01:10 -08:00
edwardcwang
8a30579a3e
Support firrtl output in command line for MacroCompiler ( #28 )
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* Use the given port prefix (fix a bug preventing two unit tests from passing)
* Support firrtl output in addition to Verilog
2017-12-04 15:12:42 -08:00
edwardcwang
c884a2fb15
Correct multi-ported memory compilation ( #27 )
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* Correct multi-ported memory compilation
It was incorrectly splitting multiple times before. Fixed the issue and
added regression tests for this issue.
* Add 1 read 1 write test
2017-10-06 18:04:49 -07:00
Edward Wang
bc26f5eb1a
Address review comments
2017-10-03 11:56:30 -07:00
Edward Wang
13d8a0f8f5
Add strict mode
2017-10-03 11:56:30 -07:00
Edward Wang
43d242707b
Enable some more tests
2017-10-03 11:56:30 -07:00
Edward Wang
af67540a81
Add test from Donggyu
2017-10-03 11:56:30 -07:00
Edward Wang
5d3bebd2b9
Re-implement parallel mapping
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- Support byte-masked SRAM, yay
- Also nuke a bunch of bugs
2017-10-03 11:56:30 -07:00
Edward Wang
676b8e72ba
Add rocket-chip inspired tests
2017-10-03 11:56:30 -07:00
Edward Wang
e89079f2d7
Test for non-empty Verilog
2017-10-03 11:56:30 -07:00
Edward Wang
df8b5815c6
Trim redundant MDF field
2017-10-03 11:56:30 -07:00
Edward Wang
4013b1924f
Implement command line cost metric selection
2017-10-03 11:56:30 -07:00
Edward Wang
0f4683700f
Add cost function selection test
2017-10-03 11:56:30 -07:00
Edward Wang
0203aa9e7c
Move notes to main file since they apply there as well
2017-10-03 11:56:30 -07:00
Edward Wang
f854c6c9f0
Nuke hardcoded JSON tests from orbit
2017-10-03 11:56:30 -07:00
Edward Wang
a177c895e8
Finish rewriting in new format
2017-10-03 11:56:30 -07:00
Edward Wang
513da4eb37
Support non-prefixed ports
2017-10-03 11:56:30 -07:00
Edward Wang
519ffef50a
Tests aren't that brittle since firrtl reparses the output
2017-10-03 11:56:30 -07:00
Edward Wang
e47cf92139
Move HasNoLibTestGenerator out of SynFlops
2017-10-03 11:56:30 -07:00
Edward Wang
94b13e96fb
Add functional tests
...
To be enabled when a new firrtl-interpreter is published
2017-10-03 11:56:30 -07:00
Edward Wang
de66405fe8
Write flop tests using generator
2017-10-03 11:56:30 -07:00
Edward Wang
93331cd26d
More refactor
2017-10-03 11:56:30 -07:00
Edward Wang
3730f76fa3
Fix unit tests to include address registers
2017-10-03 11:56:30 -07:00
Edward Wang
e3d5e4d3ad
Refactor execution of the compiler from the check
2017-10-03 11:56:30 -07:00
Edward Wang
cca6c0ea7e
Refactor memory compiler, again
2017-10-03 11:56:30 -07:00
Edward Wang
b546f49a85
Fix tests by reordering statements
...
Not sure what caused this re-ordering but it doesn't seem to affect anything?
2017-10-03 11:56:30 -07:00
Edward Wang
2126835df2
Clarify comments
2017-10-03 11:56:30 -07:00
Edward Wang
e02f885e4b
Port all tests to use the generator
2017-10-03 11:56:30 -07:00
Edward Wang
2a8d8803a9
Further refactor test generator
2017-10-03 11:56:30 -07:00
Edward Wang
0bfc7a94df
Make instance numbers generic for depth and width
2017-10-03 11:56:30 -07:00
Edward Wang
484906b85c
Refactor test generator from depth
2017-10-03 11:56:30 -07:00
Edward Wang
dd4c55aa09
Implement the rest of the split depth tests
2017-10-03 11:56:30 -07:00
Edward Wang
d83fb47da3
Add split port tests
2017-10-03 11:56:30 -07:00
Edward Wang
870e3c1af1
All depth tests now fully automatic
2017-10-03 11:56:30 -07:00
Edward Wang
ae139ede44
Fix another name collision
2017-10-03 11:56:30 -07:00
Edward Wang
79f73311d8
Uniquify names
2017-10-03 11:56:30 -07:00
Edward Wang
9670d76a3d
Moar SRAM generators, yum yum
2017-10-03 11:56:30 -07:00
Donggyu Kim
9de1f5f2c0
restructure macros for better submoduling
2017-10-03 11:56:30 -07:00
