Implement the rest of the split depth tests

macros/src/test/scala/SimpleSplitDepth.scala

@@ -406,9 +406,9 @@ class SplitDepth_SplitPortsNonMasked extends MacroCompilerSpec with HasSRAMGener
   import mdf.macrolib._
 
   "Non-masked split lib; split mem" should "split fine" in {
-    val lib = "lib-split_depth-rw-split-lib-split-mem.json"
-    val mem = "mem-split_depth-rw-split-lib-split-mem.json"
-    val v = "split_depth-rw-split-lib-split-mem.v"
+    val lib = "lib-split_depth-r-w-split-lib-split-mem.json"
+    val mem = "mem-split_depth-r-w-split-lib-split-mem.json"
+    val v = "split_depth-r-w-split-lib-split-mem.v"
 
     val libMacro = SRAMMacro(
       macroType=SRAM,
@@ -493,9 +493,9 @@ circuit target_memory :
     // Right now all we can get is a "port count must match" error.
     pending
 
-    val lib = "lib-split_depth-r-mw-regular-lib-split-mem.json"
-    val mem = "mem-split_depth-r-mw-regular-lib-split-mem.json"
-    val v = "split_depth-r-mw-regular-lib-split-mem.v"
+    val lib = "lib-split_depth-r-w-regular-lib-split-mem.json"
+    val mem = "mem-split_depth-r-w-regular-lib-split-mem.json"
+    val v = "split_depth-r-w-regular-lib-split-mem.v"
 
     val memMacro = SRAMMacro(
       macroType=SRAM,
@@ -528,9 +528,9 @@ TODO
     // [edwardw]: does this even make sense? Can we compile a 2-ported memory using 1-ported memories?
     pending
 
-    val lib = "lib-split_depth-rw-split-lib-regular-mem.json"
-    val mem = "mem-split_depth-rw-split-lib-regular-mem.json"
-    val v = "split_depth-rw-split-lib-regular-mem.v"
+    val lib = "lib-split_depth-r-w-split-lib-regular-mem.json"
+    val mem = "mem-split_depth-r-w-split-lib-regular-mem.json"
+    val v = "split_depth-r-w-split-lib-regular-mem.v"
 
     val libMacro = SRAMMacro(
       macroType=SRAM,
@@ -556,3 +556,172 @@ TODO
     execute(mem, lib, false, output)
   }
 }
+
+// Split read and (masked) write ports (r+mw).
+class SplitDepth_SplitPortsMasked extends MacroCompilerSpec with HasSRAMGenerator {
+  lazy val width = 8
+  lazy val mem_depth = 2048
+  lazy val lib_depth = 1024
+  lazy val mem_maskGran = Some(8)
+  lazy val lib_maskGran = Some(1)
+
+  override val memPrefix = testDir
+  override val libPrefix = testDir
+
+  import mdf.macrolib._
+
+  "Masked split lib; split mem" should "split fine" in {
+    val lib = "lib-split_depth-r-mw-split-lib-split-mem.json"
+    val mem = "mem-split_depth-r-mw-split-lib-split-mem.json"
+    val v = "split_depth-r-mw-split-lib-split-mem.v"
+
+    val libMacro = SRAMMacro(
+      macroType=SRAM,
+      name="awesome_lib_mem",
+      width=width,
+      depth=lib_depth,
+      family="1r1w",
+      ports=Seq(
+        generateReadPort("innerA", width, lib_depth),
+        generateWritePort("innerB", width, lib_depth, lib_maskGran)
+      )
+    )
+
+    val memMacro = SRAMMacro(
+      macroType=SRAM,
+      name="target_memory",
+      width=width,
+      depth=mem_depth,
+      family="1r1w",
+      ports=Seq(
+        generateReadPort("outerB", width, mem_depth),
+        generateWritePort("outerA", width, mem_depth, mem_maskGran)
+      )
+    )
+
+    writeToLib(mem, Seq(memMacro))
+    writeToLib(lib, Seq(libMacro))
+
+    val output =
+"""
+circuit target_memory :
+  module target_memory :
+    input outerB_clk : Clock
+    input outerB_addr : UInt<11>
+    output outerB_dout : UInt<8>
+    input outerA_clk : Clock
+    input outerA_addr : UInt<11>
+    input outerA_din : UInt<8>
+    input outerA_write_en : UInt<1>
+    input outerA_mask : UInt<1>
+
+    node outerB_addr_sel = bits(outerB_addr, 10, 10)
+    node outerA_addr_sel = bits(outerA_addr, 10, 10)
+    inst mem_0_0 of awesome_lib_mem
+    mem_0_0.innerA_clk <= outerB_clk
+    mem_0_0.innerA_addr <= outerB_addr
+    node outerB_dout_0_0 = bits(mem_0_0.innerA_dout, 7, 0)
+    node outerB_dout_0 = outerB_dout_0_0
+    mem_0_0.innerB_clk <= outerA_clk
+    mem_0_0.innerB_addr <= outerA_addr
+    mem_0_0.innerB_din <= bits(outerA_din, 7, 0)
+    mem_0_0.innerB_mask <= cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), bits(outerA_mask, 0, 0))))))))
+    mem_0_0.innerB_write_en <= and(and(outerA_write_en, UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h0")))
+    inst mem_1_0 of awesome_lib_mem
+    mem_1_0.innerA_clk <= outerB_clk
+    mem_1_0.innerA_addr <= outerB_addr
+    node outerB_dout_1_0 = bits(mem_1_0.innerA_dout, 7, 0)
+    node outerB_dout_1 = outerB_dout_1_0
+    mem_1_0.innerB_clk <= outerA_clk
+    mem_1_0.innerB_addr <= outerA_addr
+    mem_1_0.innerB_din <= bits(outerA_din, 7, 0)
+    mem_1_0.innerB_mask <= cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), bits(outerA_mask, 0, 0))))))))
+    mem_1_0.innerB_write_en <= and(and(outerA_write_en, UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h1")))
+    outerB_dout <= mux(eq(outerB_addr_sel, UInt<1>("h0")), outerB_dout_0, mux(eq(outerB_addr_sel, UInt<1>("h1")), outerB_dout_1, UInt<1>("h0")))
+
+  extmodule awesome_lib_mem :
+    input innerA_clk : Clock
+    input innerA_addr : UInt<10>
+    output innerA_dout : UInt<8>
+    input innerB_clk : Clock
+    input innerB_addr : UInt<10>
+    input innerB_din : UInt<8>
+    input innerB_write_en : UInt<1>
+    input innerB_mask : UInt<8>
+
+    defname = awesome_lib_mem
+"""
+
+    compile(mem, lib, v, false)
+    execute(mem, lib, false, output)
+  }
+
+  "Non-masked regular lib; split mem" should "split fine" in {
+    // Enable this test when the memory compiler can compile non-matched
+    // memories (e.g. mrw mem and r+mw lib).
+    // Right now all we can get is a "port count must match" error.
+    pending
+
+    val lib = "lib-split_depth-r-mw-regular-lib-split-mem.json"
+    val mem = "mem-split_depth-r-mw-regular-lib-split-mem.json"
+    val v = "split_depth-r-mw-regular-lib-split-mem.v"
+
+    val memMacro = SRAMMacro(
+      macroType=SRAM,
+      name="target_memory",
+      width=width,
+      depth=mem_depth,
+      family="1r1w",
+      ports=Seq(
+        generateReadPort("outerB", width, mem_depth),
+        generateWritePort("outerA", width, mem_depth, mem_maskGran)
+      )
+    )
+
+    writeToLib(mem, Seq(memMacro))
+    writeToLib(lib, Seq(generateSRAM("awesome_lib_mem", "lib", width, lib_depth, lib_maskGran)))
+
+    val output =
+"""
+TODO
+"""
+
+    compile(mem, lib, v, false)
+    execute(mem, lib, false, output)
+  }
+
+  "Non-masked split lib; regular mem" should "split fine" in {
+    // Enable this test when the memory compiler can compile non-matched
+    // memories (e.g. mrw mem and r+mw lib).
+    // Right now all we can get is a "port count must match" error.
+    // [edwardw]: does this even make sense? Can we compile a 2-ported memory using 1-ported memories?
+    pending
+
+    val lib = "lib-split_depth-r-mw-split-lib-regular-mem.json"
+    val mem = "mem-split_depth-r-mw-split-lib-regular-mem.json"
+    val v = "split_depth-r-mw-split-lib-regular-mem.v"
+
+    val libMacro = SRAMMacro(
+      macroType=SRAM,
+      name="awesome_lib_mem",
+      width=width,
+      depth=lib_depth,
+      family="1rw",
+      ports=Seq(
+        generateReadPort("innerA", width, lib_depth),
+        generateWritePort("innerB", width, lib_depth, lib_maskGran)
+      )
+    )
+
+    writeToLib(mem, Seq(generateSRAM("target_memory", "outer", width, mem_depth, mem_maskGran)))
+    writeToLib(lib, Seq(libMacro))
+
+    val output =
+"""
+TODO
+"""
+
+    compile(mem, lib, v, false)
+    execute(mem, lib, false, output)
+  }
+}