Hansung Kim
3dc58def3c
Add parallel flag to VCS/Verilator C compilation
2024-05-07 16:18:30 -07:00
Richard Yan
d0b274ab78
Merge branch 'main' of https://github.com/ucb-bar/chipyard into ucb-bar-main
2024-04-20 02:03:35 -07:00
Richard Yan
e75c77a08a
synthesizable radiance
2024-04-17 18:22:44 -07:00
Hansung Kim
f77f1edecc
Add fpnew packages and include dirs to vcs flags
...
This is necessary because Verilog package definitions need to be compiled before
the modules that reference them, but the compilation order is not enforced with
addResource()s.
2024-04-15 15:31:10 -07:00
Jerry Zhao
4ce6198b86
Pass -top flag to VCS to avoid simulating non-tops
2024-03-19 23:49:08 -07:00
Jerry Zhao
7b3d3e54bd
Add incdirs to vcs/verilator flows
2024-03-19 23:48:51 -07:00
Hansung Kim
3190224cfe
Squelch inout coerce lint messages from vortex RTL
2024-01-16 16:32:30 -08:00
Jerry Zhao
4da1dea50f
Support multi-binary-run in RTL sim
2023-05-24 16:48:18 -07:00
Jerry Zhao and GitHub
a0569208a5
Fix VCS waveforms
2023-05-10 15:49:59 -07:00
abejgonzalez
95349755b5
Support TestDriver.v as top
2023-03-13 11:11:23 -07:00
Hansung Kim