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Author SHA1 Message Date
Colin SchmidtandGitHub c96a5e5f44 Print the firrtl exception if we get one 
Fixes #67
 2019-10-24 14:55:03 -07:00
Albert Magyar 76ccb75b00 Filter out all deleted annotations 2019-08-19 09:08:30 -07:00
Abraham Gonzalez 76f6c8adb2 remove large annotations 2019-08-17 10:35:41 -07:00
Albert MagyarandGitHub 26096e07f6 Coordinate Top and Harness generation (#63) 
* Coordinate Top and Harness generation

* Update to use .f filename override annotations

* Move top generation to def to help GC
 2019-07-30 22:42:05 -07:00
Albert MagyarandGitHub e3c822709b Filter all EmittedAnnotations from JSON emission (#64) 
* Filter all EmittedAnnotations from JSON emission

* Filter more annotations
 2019-07-29 20:39:07 -07:00
John WrightandColin Schmidt 82636b3ff4 Upstream MemConf and use it (with some slight tweaks) 2019-05-14 10:10:47 -07:00
Colin SchmidtandColin Schmidt c23b2b6f84 SRAM depth to bigint 
max synflop depth support
Fix annotation mangling on the harness side
 2019-05-14 10:10:47 -07:00
John WrightandGitHub e548210ef4 Add options to emit top/harness firrtl and annotations (#54) 2019-03-29 13:55:18 -07:00
Colin SchmidtandGitHub 8f7af5b0bf Fix annos (#53) 
* Fixes #36 by using the renamemap
* Also fix harness passes annotation handling h/t azidar
* Remove old comment
 2019-03-27 17:20:41 -07:00
Colin Schmidtandedwardcwang affd033f0a Emit hammer IR from MacroCompiler (#50) 2019-03-25 22:52:39 -07:00
Colin SchmidtandGitHub fdad525007 HighForm has whens so we need to check for instances there (#49) 
Fixes a bug
 2019-03-18 11:25:58 -07:00
Abraham GonzalezandColin Schmidt 817726ff1f stop exceptions on empty conf files (#43) 
* stop exceptions on empty conf files

* emit empty verilog file | warn users

* put else's on same line as closing bracket
 2019-03-18 10:15:50 -07:00
Colin SchmidtandGitHub de94c2376a Add Travis (#48) 2019-03-18 10:07:10 -07:00
Colin Schmidtandedwardcwang f5b452229a Avoid using the github redirect for mdf 2019-03-18 09:25:59 -07:00
Colin SchmidtandColin Schmidt 0b9d74ada7 Fix unit tests update cost function once more 
bump mdf to master
 2019-03-18 07:25:04 -07:00
Colin SchmidtandColin Schmidt 44e97826d4 Fix cost metric for non Compiler libs 
Also a small fix from reviewer
 2019-03-18 07:25:04 -07:00
Colin SchmidtandColin Schmidt 6cdf978a6d Fix forms of passes to happen before replseqmem 
This ensures the conf file doesn't have any testharness
memories, which are too big and break downstream tools
 2019-03-18 07:25:04 -07:00
Colin SchmidtandColin Schmidt 98a410812c Filter compiler libraries before mapping 
The filter is always by family and maskability and then by any
integral mappings.
 2019-03-18 07:25:04 -07:00
Colin SchmidtandColin Schmidt a0510e6664 Change cost to double from BigInt and fix default metric 
I don't think it was adding anything and now we can get rid of
the weird +1/-1
 2019-03-18 07:25:04 -07:00
Colin SchmidtandColin Schmidt 45278a6de0 Make SRAM per port clocks optional 
Connects to whatever clock ports are available
 2019-03-18 07:25:04 -07:00
Colin Schmidt a10a6cca35 Add SimDTM to list of extmodules 2019-03-01 18:52:41 -08:00
James DunnandJohn Wright 9d505d6063 Fixed index offset in mask port mapping. (#38) 
Fixed index offset in mask port mapping.
 2019-02-13 15:17:12 -08:00
John WrightandJohn Wright 1f58ea1e14 Style/Comments from review of #35 2019-02-13 10:15:51 -08:00
John WrightandJohn Wright efd2f09b21 Naming consistency (memMode -> memFormat) 2019-02-13 10:15:51 -08:00
John WrightandJohn Wright f0c7bab3ea Use the correct 'magic values' for the port names 
Ensure backwards compatiblity by using -m for MDF input and -n for conf
input. Also fix the naming scheme for memory ports.
 2019-02-13 10:15:51 -08:00
John WrightandJohn Wright d861fdd95c Don't run DCE && Profit 2019-02-13 10:15:51 -08:00
John WrightandJohn Wright 12842cb3a7 Add MemConf and change MacroCompiler to use a conf file instead of MDF JSON 2019-02-13 10:15:51 -08:00
John WrightandJohn Wright 79b8fd324b This compiles and works correctly, but is kind of hacky, and will break as soon as any additional external/blackbox modules are added to the test harness. The test harness should detect external modules and not rename them instead of what is happening here. 2019-02-13 10:15:51 -08:00
John WrightandJohn Wright c8efc5e88b Refactor the harness generation; use upstream arguments and passes where appropriate 2019-02-13 10:15:51 -08:00
Paul RiggeandJohn Wright 22e6d9c5d4 Fix repl-seq-mem 2019-02-13 10:15:51 -08:00
Paul RiggeandJohn Wright 7bbf7f00f6 Run transforms in slightly different order 
Also, don't rename TestHarness.
 2019-02-13 10:15:51 -08:00
Paul RiggeandJohn Wright 801abd98bb Fix null pointer exception in options parser 2019-02-13 10:15:51 -08:00
Paul RiggeandJohn Wright f310d45381 Refactor barstools for new versions of things. 
- No handlebars (not being published for Scala 2.12)
- Update for new annotations APIs

Bump sbt-dependency-graph to 0.9.2 for this scala version
 2019-02-13 10:15:51 -08:00
Edward Wangandedwardcwang 4727d475c7 Add options to force certain memories to lib or synflops 2019-02-06 12:40:53 -08:00
Edward Wangandedwardcwang d1c1b3fba6 Overhaul CompilerMode parsing 2019-02-06 12:40:53 -08:00
edwardcwangandGitHub 74ca2bc491 Remove deprecated run-main 2018-10-31 13:47:28 -07:00
edwardcwangandGitHub 93bf7895be Fix corner case in compiling a small mem using a large lib (#32) 
* Refactor bit pairs calculation into a separate function

* Minor clarifications

* Clarify MacroCompilerSpec helpers

* Add SmallTagArrayTest test

* Fix corner case in compiling a small mem using a large lib
 2018-04-26 10:33:55 -07:00
edwardcwangandGitHub f7634b82cd Include macro compiler JAR compilation instructions 2018-03-21 14:50:18 -07:00
Edward Wang 1ccd8f6dbc Bump mdf to match master 2018-02-16 16:03:08 -08:00
Adam IzraelevitzandGitHub 79c8c283cc Add memory compiler to macros (#29) 
* Add memory compiler to macros

* Removed weird spacing

* Make sramcompiler width/depth range inclusive

* Added sramcompiler test
 2018-02-16 16:01:10 -08:00
edwardcwangandGitHub 8a30579a3e Support firrtl output in command line for MacroCompiler (#28) 
* Use the given port prefix (fix a bug preventing two unit tests from passing)
* Support firrtl output in addition to Verilog
 2017-12-04 15:12:42 -08:00
edwardcwangandGitHub c884a2fb15 Correct multi-ported memory compilation (#27) 
* Correct multi-ported memory compilation

It was incorrectly splitting multiple times before. Fixed the issue and
added regression tests for this issue.

* Add 1 read 1 write test
 2017-10-06 18:04:49 -07:00
Edward Wangandedwardcwang e1499fcdc0 Update command line help 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang c91d98d5b3 Bump mdf for the last time, for now 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang e09f8b1b0d Fix grammar 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang bc26f5eb1a Address review comments 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang d2b105079d Not a scaladoc 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 4eca53ba55 Bump mdf again 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 13d8a0f8f5 Add strict mode 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 11bd81165b Bump mdf 2017-10-03 11:56:30 -07:00