Fix sbt assembly (remove duplicate classes, fix conflicts)

This commit is contained in:
abejgonzalez
2023-03-03 15:36:36 -08:00
parent 8c8820a678
commit fd62d9ec2d
7 changed files with 32 additions and 19 deletions

View File

@@ -4,14 +4,37 @@ import Tests._
// implicit one
lazy val chipyardRoot = Project("chipyardRoot", file("."))
// keep chisel/firrtl specific class files, drop other conflicts
val chiselFirrtlMergeStrategy = CustomMergeStrategy("cfmergestrategy") { deps =>
import sbtassembly.Assembly.{Project, Library}
val keepDeps = deps.filter { dep =>
val nm = dep match {
case p: Project => p.name
case l: Library => l.moduleCoord.name
}
Seq("firrtl", "chisel3").contains(nm.split("_")(0)) // split by _ to avoid checking on major/minor version
}
if (keepDeps.size <= 1) {
Right(keepDeps.map(dep => JarEntry(dep.target, dep.stream)))
} else {
Left(s"Unable to resolve conflict (${keepDeps.size}>1 conflicts):\n${keepDeps.mkString("\n")}")
}
}
lazy val commonSettings = Seq(
organization := "edu.berkeley.cs",
version := "1.6",
scalaVersion := "2.13.10",
assembly / test := {},
assembly / assemblyMergeStrategy := { _ match {
case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard
case _ => MergeStrategy.first}},
assembly / assemblyMergeStrategy := {
case PathList("chisel3", "stage", xs @ _*) => chiselFirrtlMergeStrategy
case PathList("firrtl", "stage", xs @ _*) => chiselFirrtlMergeStrategy
// should be safe in JDK11: https://stackoverflow.com/questions/54834125/sbt-assembly-deduplicate-module-info-class
case x if x.endsWith("module-info.class") => MergeStrategy.discard
case x =>
val oldStrategy = (assembly / assemblyMergeStrategy).value
oldStrategy(x)
},
scalacOptions ++= Seq(
"-deprecation",
"-unchecked",
@@ -86,8 +109,6 @@ lazy val hardfloat = (project in rocketChipDir / "hardfloat")
.settings(commonSettings)
.settings(
libraryDependencies ++= Seq(
"org.scala-lang" % "scala-reflect" % scalaVersion.value,
"org.json4s" %% "json4s-jackson" % "3.6.6",
"org.scalatest" %% "scalatest" % "3.2.0" % "test"
)
)
@@ -97,20 +118,11 @@ lazy val rocketMacros = (project in rocketChipDir / "macros")
.settings(
libraryDependencies ++= Seq(
"org.scala-lang" % "scala-reflect" % scalaVersion.value,
"org.json4s" %% "json4s-jackson" % "3.6.6",
"org.scalatest" %% "scalatest" % "3.2.0" % "test"
)
)
lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/build-rules/sbt")
.settings(commonSettings)
.settings(
libraryDependencies ++= Seq(
"org.scala-lang" % "scala-reflect" % scalaVersion.value,
"org.json4s" %% "json4s-jackson" % "3.6.6",
"org.scalatest" %% "scalatest" % "3.2.0" % "test"
)
)
lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
.dependsOn(hardfloat, rocketMacros, rocketConfig)
@@ -230,7 +242,6 @@ lazy val iocell = Project(id = "iocell", base = file("./tools/barstools/") / "sr
lazy val tapeout = (project in file("./tools/barstools/"))
.settings(chiselSettings)
.settings(chiselTestSettings)
.enablePlugins(sbtassembly.AssemblyPlugin)
.settings(commonSettings)
lazy val dsptools = freshProject("dsptools", file("./tools/dsptools"))

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@@ -99,9 +99,11 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip
# compile scala jars
#########################################################################################
$(GEN_CLASSPATH_TARGETS) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS)
mkdir -p $(dir $@)
$(call run_sbt_assembly,$(SBT_PROJECT),$(GEN_CLASSPATH))
$(BTL_CLASSPATH_TARGETS) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS)
mkdir -p $(dir $@)
$(call run_sbt_assembly,tapeout,$(BTL_CLASSPATH))
#########################################################################################

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@@ -47,7 +47,7 @@ debug: $(sim_debug)
# simulaton requirements
#########################################################################################
SIM_FILE_REQS += \
$(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \
$(CHIPYARD_RSRCS_DIR)/csrc/cy-emulator.cc \
$(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h \
# the following files are needed for emulator.cc to compile (even if they aren't part of the RTL build)