diff --git a/build.sbt b/build.sbt
index 0f065836..ff55f1db 100644
--- a/build.sbt
+++ b/build.sbt
@@ -4,14 +4,37 @@ import Tests._
 // implicit one
 lazy val chipyardRoot = Project("chipyardRoot", file("."))
 
+// keep chisel/firrtl specific class files, drop other conflicts
+val chiselFirrtlMergeStrategy = CustomMergeStrategy("cfmergestrategy") { deps =>
+  import sbtassembly.Assembly.{Project, Library}
+  val keepDeps = deps.filter { dep =>
+    val nm = dep match {
+      case p: Project => p.name
+      case l: Library => l.moduleCoord.name
+    }
+    Seq("firrtl", "chisel3").contains(nm.split("_")(0)) // split by _ to avoid checking on major/minor version
+  }
+  if (keepDeps.size <= 1) {
+    Right(keepDeps.map(dep => JarEntry(dep.target, dep.stream)))
+  } else {
+    Left(s"Unable to resolve conflict (${keepDeps.size}>1 conflicts):\n${keepDeps.mkString("\n")}")
+  }
+}
+
 lazy val commonSettings = Seq(
   organization := "edu.berkeley.cs",
   version := "1.6",
   scalaVersion := "2.13.10",
   assembly / test := {},
-  assembly / assemblyMergeStrategy := { _ match {
-    case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard
-    case _ => MergeStrategy.first}},
+  assembly / assemblyMergeStrategy := {
+    case PathList("chisel3", "stage", xs @ _*) => chiselFirrtlMergeStrategy
+    case PathList("firrtl", "stage", xs @ _*) => chiselFirrtlMergeStrategy
+    // should be safe in JDK11: https://stackoverflow.com/questions/54834125/sbt-assembly-deduplicate-module-info-class
+    case x if x.endsWith("module-info.class") => MergeStrategy.discard
+    case x =>
+      val oldStrategy = (assembly / assemblyMergeStrategy).value
+      oldStrategy(x)
+  },
   scalacOptions ++= Seq(
     "-deprecation",
     "-unchecked",
@@ -86,8 +109,6 @@ lazy val hardfloat  = (project in rocketChipDir / "hardfloat")
   .settings(commonSettings)
   .settings(
     libraryDependencies ++= Seq(
-      "org.scala-lang" % "scala-reflect" % scalaVersion.value,
-      "org.json4s" %% "json4s-jackson" % "3.6.6",
       "org.scalatest" %% "scalatest" % "3.2.0" % "test"
     )
   )
@@ -97,20 +118,11 @@ lazy val rocketMacros  = (project in rocketChipDir / "macros")
   .settings(
     libraryDependencies ++= Seq(
       "org.scala-lang" % "scala-reflect" % scalaVersion.value,
-      "org.json4s" %% "json4s-jackson" % "3.6.6",
-      "org.scalatest" %% "scalatest" % "3.2.0" % "test"
     )
   )
 
 lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/build-rules/sbt")
   .settings(commonSettings)
-  .settings(
-    libraryDependencies ++= Seq(
-      "org.scala-lang" % "scala-reflect" % scalaVersion.value,
-      "org.json4s" %% "json4s-jackson" % "3.6.6",
-      "org.scalatest" %% "scalatest" % "3.2.0" % "test"
-    )
-  )
 
 lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
   .dependsOn(hardfloat, rocketMacros, rocketConfig)
@@ -230,7 +242,6 @@ lazy val iocell = Project(id = "iocell", base = file("./tools/barstools/") / "sr
 lazy val tapeout = (project in file("./tools/barstools/"))
   .settings(chiselSettings)
   .settings(chiselTestSettings)
-  .enablePlugins(sbtassembly.AssemblyPlugin)
   .settings(commonSettings)
 
 lazy val dsptools = freshProject("dsptools", file("./tools/dsptools"))
diff --git a/common.mk b/common.mk
index f61a043b..54c1644e 100644
--- a/common.mk
+++ b/common.mk
@@ -99,9 +99,11 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip
 # compile scala jars
 #########################################################################################
 $(GEN_CLASSPATH_TARGETS) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS)
+	mkdir -p $(dir $@)
 	$(call run_sbt_assembly,$(SBT_PROJECT),$(GEN_CLASSPATH))
 
 $(BTL_CLASSPATH_TARGETS) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS)
+	mkdir -p $(dir $@)
 	$(call run_sbt_assembly,tapeout,$(BTL_CLASSPATH))
 
 #########################################################################################
diff --git a/generators/chipyard/src/main/resources/csrc/emulator.cc b/generators/chipyard/src/main/resources/csrc/cy-emulator.cc
similarity index 100%
rename from generators/chipyard/src/main/resources/csrc/emulator.cc
rename to generators/chipyard/src/main/resources/csrc/cy-emulator.cc
diff --git a/generators/cva6 b/generators/cva6
index 737fd83b..6a6184f2 160000
--- a/generators/cva6
+++ b/generators/cva6
@@ -1 +1 @@
-Subproject commit 737fd83b820aea6d615f372a97766b1d390a18d5
+Subproject commit 6a6184f292ea2b81fcc5b3d5186fa31075c1d240
diff --git a/generators/riscv-sodor b/generators/riscv-sodor
index d6ccc5de..1b169845 160000
--- a/generators/riscv-sodor
+++ b/generators/riscv-sodor
@@ -1 +1 @@
-Subproject commit d6ccc5de5cf6f07be500a0d1351656bb0c50e4a3
+Subproject commit 1b169845e370e61f9cb765451a37ffc2323719bd
diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile
index d48da28e..098326be 100644
--- a/sims/verilator/Makefile
+++ b/sims/verilator/Makefile
@@ -47,7 +47,7 @@ debug: $(sim_debug)
 # simulaton requirements
 #########################################################################################
 SIM_FILE_REQS += \
-	$(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \
+	$(CHIPYARD_RSRCS_DIR)/csrc/cy-emulator.cc \
 	$(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h \
 
 # the following files are needed for emulator.cc to compile (even if they aren't part of the RTL build)
diff --git a/tools/barstools b/tools/barstools
index 30900965..fe81afec 160000
--- a/tools/barstools
+++ b/tools/barstools
@@ -1 +1 @@
-Subproject commit 30900965f0cc2d5046e2160dd9c700805a8e0542
+Subproject commit fe81afec14634316606a9dd10628c220d53bd256