diff --git a/tapeout/src/main/scala/transforms/ResetInverter.scala b/tapeout/src/main/scala/transforms/ResetInverter.scala
index 2cbbd45a..22b2a704 100644
--- a/tapeout/src/main/scala/transforms/ResetInverter.scala
+++ b/tapeout/src/main/scala/transforms/ResetInverter.scala
@@ -24,7 +24,8 @@ object ResetN extends Pass {
       "Can only invert reset on a module with reset!")
     // Rename "reset" to "reset_n"
     val portsx = mod.ports map {
-      case Port(info, "reset", Input, Bool) => Port(info, "reset_n", Input, Bool)
+      case Port(info, "reset", Input, Bool) =>
+        Port(info, "reset_n", Input, Bool)
       case other => other
     }
     val newReset = DefNode(NoInfo, "reset", DoPrim(Not, Seq(Reference("reset_n", Bool)), Seq.empty, Bool))
diff --git a/tapeout/src/test/scala/transforms/ResetInverterSpec.scala b/tapeout/src/test/scala/transforms/ResetInverterSpec.scala
index 4b5de967..fe204288 100644
--- a/tapeout/src/test/scala/transforms/ResetInverterSpec.scala
+++ b/tapeout/src/test/scala/transforms/ResetInverterSpec.scala
@@ -19,13 +19,15 @@ class ExampleModuleNeedsResetInverted extends Module with ResetInverter {
 }
 
 class ResetNSpec extends FreeSpec with Matchers {
-  "Inverting reset needs to be done throughout module" in {
-    val chirrtl = (new ChiselStage).emitChirrtl(new ExampleModuleNeedsResetInverted, Array())
+  "Inverting reset needs to be done throughout module in Chirrtl" in {
+    val chirrtl = (new ChiselStage).emitChirrtl(new ExampleModuleNeedsResetInverted, Array("--no-run-firrtl"))
     chirrtl should include("input reset :")
     (chirrtl should not).include("input reset_n :")
     (chirrtl should not).include("node reset = not(reset_n)")
+  }
 
-    val firrtl = (new ChiselStage).emitFirrtl(new ExampleModuleNeedsResetInverted, Array("-X", "low"))
+  "Inverting reset needs to be done throughout module when generating firrtl" in {
+    val firrtl = (new ChiselStage).emitFirrtl(new ExampleModuleNeedsResetInverted)
     firrtl should include("input reset_n :")
     firrtl should include("node reset = not(reset_n)")
     (firrtl should not).include("input reset :")