Merge pull request #778 from ucb-bar/jerryz123-patch-2

Update comment on GenerateReset
2021-01-30 19:53:45 -08:00
parent f22051ca84 99a1c5d542
commit ec14bf0d23
1 changed files with 2 additions and 2 deletions
--- a/generators/chipyard/src/main/scala/Clocks.scala
+++ b/generators/chipyard/src/main/scala/Clocks.scala
@@ -17,8 +17,8 @@ import chipyard.clocking._

 /**
 * A simple reset implementation that punches out reset ports
- * for standard Module classes. Three basic reset schemes
- * are provided. See [[GlobalResetScheme]].
+ * for standard Module classes. The ChipTop reset pin is Async.
+ * Synchronization is performed in the ClockGroupResetSynchronizer
 */
 object GenerateReset {
  def apply(chiptop: ChipTop, clock: Clock): Reset = {