From 99a1c5d54217a110d03b36374383fff08f55a723 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Sat, 30 Jan 2021 19:47:27 -0800
Subject: [PATCH] Update comment on GenerateReset

ChipTop reset was standardized to be async for 1.4.0
---
 generators/chipyard/src/main/scala/Clocks.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala
index e4d48b59..9ca6a801 100644
--- a/generators/chipyard/src/main/scala/Clocks.scala
+++ b/generators/chipyard/src/main/scala/Clocks.scala
@@ -17,8 +17,8 @@ import chipyard.clocking._
 
 /**
  * A simple reset implementation that punches out reset ports
- * for standard Module classes. Three basic reset schemes
- * are provided. See [[GlobalResetScheme]].
+ * for standard Module classes. The ChipTop reset pin is Async.
+ * Synchronization is performed in the ClockGroupResetSynchronizer
  */
 object GenerateReset {
   def apply(chiptop: ChipTop, clock: Clock): Reset = {