Generator unification
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@@ -60,19 +60,6 @@ class WithBoomTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
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case MaxHartIdBits => log2Ceil(params.size + up(TraceGenKey, site).length) max 1
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})
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class TraceGenConfig extends Config(
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new WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++
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new BaseConfig)
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class NonBlockingTraceGenConfig extends Config(
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new WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
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new BaseConfig)
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class BoomTraceGenConfig extends Config(
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new WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++
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new BaseConfig)
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class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
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extends Config((site, here, up) => {
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case TraceGenKey => params.map { dcp => TraceGenParams(
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@@ -100,7 +87,3 @@ class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
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case MaxHartIdBits => if (params.size == 1) 1 else log2Ceil(params.size)
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})
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class NonBlockingTraceGenL2Config extends Config(
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new WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++
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new WithInclusiveCache ++
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new BaseConfig)
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@@ -1,27 +0,0 @@
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package tracegen
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import chisel3._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy.LazyModule
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import freechips.rocketchip.util.GeneratorApp
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class TestHarness(implicit p: Parameters) extends Module {
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val io = IO(new Bundle {
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val success = Output(Bool())
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})
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val dut = Module(LazyModule(new TraceGenSystem).module)
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io.success := dut.success
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dut.connectSimAXIMem()
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}
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object Generator extends GeneratorApp {
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// specify the name that the generator outputs files as
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override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
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// generate files
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generateFirrtl
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generateAnno
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generateTestSuiteMakefrags
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generateArtefacts
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}
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