From ebfa545344fcfea8bf17f598575b7a581c04d333 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 6 Feb 2020 20:15:09 -0800 Subject: [PATCH] Generator unification --- .circleci/config.yml | 32 ++ .circleci/defaults.sh | 4 +- .circleci/do-rtl-build.sh | 12 + .circleci/run-tests.sh | 9 +- build.sbt | 4 +- .../chipyard/src/main/scala/BoomConfigs.scala | 162 +++++++--- .../src/main/scala/ConfigMixins.scala | 128 +------- generators/chipyard/src/main/scala/GCD.scala | 11 +- .../src/main/scala/HeteroConfigs.scala | 214 ++++++------ .../chipyard/src/main/scala/IOBinders.scala | 131 ++++++++ .../chipyard/src/main/scala/InitZero.scala | 11 +- .../chipyard/src/main/scala/NodeTypes.scala | 2 +- .../src/main/scala/RocketConfigs.scala | 304 ++++++++++++------ .../chipyard/src/main/scala/TestHarness.scala | 39 +-- generators/chipyard/src/main/scala/Top.scala | 40 +-- .../chipyard/src/main/scala/TopCakes.scala | 27 -- .../src/main/scala/TracegenConfigs.scala | 35 ++ .../src/main/scala/BridgeBinders.scala | 83 +++-- .../src/main/scala/TargetConfigs.scala | 147 ++------- ...{TargetMixins.scala => TargetTraits.scala} | 0 .../firechip/src/main/scala/Targets.scala | 45 +-- generators/icenet | 2 +- generators/testchipip | 2 +- .../tracegen/src/main/scala/Configs.scala | 17 - .../tracegen/src/main/scala/TestHarness.scala | 27 -- sims/firesim | 2 +- variables.mk | 11 - 27 files changed, 815 insertions(+), 686 deletions(-) create mode 100644 generators/chipyard/src/main/scala/IOBinders.scala delete mode 100644 generators/chipyard/src/main/scala/TopCakes.scala create mode 100644 generators/chipyard/src/main/scala/TracegenConfigs.scala rename generators/firechip/src/main/scala/{TargetMixins.scala => TargetTraits.scala} (100%) delete mode 100644 generators/tracegen/src/main/scala/TestHarness.scala diff --git a/.circleci/config.yml b/.circleci/config.yml index ad5671b1..8758064e 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -226,6 +226,31 @@ jobs: - prepare-rtl: tools-version: "esp-tools" project-key: "chipyard-gemmini" + prepare-tracegen: + executor: main-env + steps: + - prepare-rtl: + project-key: "tracegen" + prepare-tracegen-boom: + executor: main-env + steps: + - prepare-rtl: + project-key: "tracegen-boom" + prepare-firesim: + executor: main-env + steps: + - prepare-rtl: + project-key: "firesim" + build-script: "do-firesim-build.sh" + prepare-fireboom: + executor: main-env + steps: + - prepare-rtl: + project-key: "fireboom" + build-script: "do-firesim-build.sh" + + + chipyard-rocket-run-tests: executor: main-env steps: @@ -284,6 +309,13 @@ jobs: run-script: "run-firesim-tests.sh" timeout: "20m" + midasexamples-run-tests: + executor: main-env + steps: + - setup-tools-verilator + - run: + name: Run midasexamples tests + command: .circleci/run-midasexamples-tests.sh # Order and dependencies of jobs to run workflows: version: 2 diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 64ed3138..6c2fdd16 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -48,7 +48,7 @@ mapping["rocketchip"]="SUB_PROJECT=rocketchip" mapping["chipyard-blkdev"]="SUB_PROJECT=chipyard CONFIG=SimBlockDeviceRocketConfig" mapping["chipyard-hwacha"]="SUB_PROJECT=chipyard CONFIG=HwachaRocketConfig" mapping["chipyard-gemmini"]="SUB_PROJECT=chipyard CONFIG=GemminiRocketConfig" -mapping["tracegen"]="SUB_PROJECT=tracegen CONFIG=NonBlockingTraceGenL2Config" -mapping["tracegen-boom"]="SUB_PROJECT=tracegen CONFIG=BoomTraceGenConfig" +mapping["tracegen"]="SUB_PROJECT=chipyard CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem" +mapping["tracegen-boom"]="SUB_PROJECT=chipyard CONFIG=BoomTraceGenConfig TOP=TraceGenSystem" mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config" mapping["fireboom"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimBoomConfig PLATFORM_CONFIG=BaseF1Config" diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 2e6384a2..5276080f 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -32,6 +32,18 @@ run "cp -r ~/.sbt $REMOTE_WORK_DIR" TOOLS_DIR=$REMOTE_RISCV_DIR LD_LIB_DIR=$REMOTE_RISCV_DIR/lib + +if [ $1 = "chipyard-gemmini" ]; then + export RISCV=$LOCAL_ESP_DIR + export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib + export PATH=$RISCV/bin:$PATH + GEMMINI_SOFTWARE_DIR=$LOCAL_SIM_DIR/../../generators/gemmini/software/gemmini-rocc-tests + cd $LOCAL_SIM_DIR/../../generators/gemmini/software + git submodule update --init --recursive gemmini-rocc-tests + cd gemmini-rocc-tests + ./build.sh +fi + if [ $1 = "chipyard-hwacha" ] || [ $1 = "chipyard-gemmini" ]; then TOOLS_DIR=$REMOTE_ESP_DIR LD_LIB_DIR=$REMOTE_ESP_DIR/lib diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index cc747756..100418aa 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -52,12 +52,11 @@ case $1 in export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib export PATH=$RISCV/bin:$PATH GEMMINI_SOFTWARE_DIR=$LOCAL_SIM_DIR/../../generators/gemmini/software/gemmini-rocc-tests - cd $GEMMINI_SOFTWARE_DIR - ./build.sh + rm -rf $GEMMINI_SOFTWARE_DIR/riscv-tests cd $LOCAL_SIM_DIR - make run-binary ${mapping[$1]} BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/aligned-baremetal - make run-binary ${mapping[$1]} BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal - make run-binary ${mapping[$1]} BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal + $LOCAL_SIM_DIR/simulator-chipyard-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/aligned-baremetal + $LOCAL_SIM_DIR/simulator-chipyard-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal + $LOCAL_SIM_DIR/simulator-chipyard-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal ;; tracegen) run_tracegen ${mapping[$1]} diff --git a/build.sbt b/build.sbt index 539f9307..678fffb5 100644 --- a/build.sbt +++ b/build.sbt @@ -123,7 +123,7 @@ lazy val testchipip = (project in file("generators/testchipip")) .settings(commonSettings) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) - .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, sha3, gemmini, icenet) + .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, sha3, gemmini, icenet, tracegen) .settings(commonSettings) lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen")) @@ -195,7 +195,7 @@ lazy val midas = ProjectRef(firesimDir, "midas") lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") lazy val firechip = (project in file("generators/firechip")) - .dependsOn(boom, hwacha, chipyard, icenet, testchipip, sifive_blocks, sifive_cache, sha3, utilities, tracegen, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") + .dependsOn(boom, hwacha, chipyard, icenet, testchipip, sifive_blocks, sifive_cache, sha3, utilities, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") .settings( commonSettings, testGrouping in Test := isolateAllTests( (definedTests in Test).value ) diff --git a/generators/chipyard/src/main/scala/BoomConfigs.scala b/generators/chipyard/src/main/scala/BoomConfigs.scala index 9eae1ea0..cd1e691b 100644 --- a/generators/chipyard/src/main/scala/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/BoomConfigs.scala @@ -8,74 +8,118 @@ import freechips.rocketchip.config.{Config} // BOOM Configs // --------------------- + class SmallBoomConfig extends Config( - new WithTSI ++ // use testchipip serial offchip link - new WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) - new WithBootROM ++ // use testchipip bootrom - new WithUART ++ // add a UART - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level mmio master port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level mmio slave port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use SiFive L2 cache - new boom.common.WithSmallBooms ++ // 1-wide BOOM - new boom.common.WithNBoomCores(1) ++ // single-core - new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter + new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts + new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) + new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing + new testchipip.WithTSI ++ // use testchipip serial offchip link + new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) + new chipyard.config.WithBootROM ++ // use default bootrom + new chipyard.config.WithUART ++ // add a UART + new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts + new boom.common.WithSmallBooms ++ // small boom config + new boom.common.WithNBoomCores(1) ++ // single-core boom + new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + class MediumBoomConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new boom.common.WithMediumBooms ++ // 2-wide BOOM + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new boom.common.WithMediumBooms ++ // medium boom config new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.system.BaseConfig) class LargeBoomConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new boom.common.WithLargeBooms ++ // 3-wide BOOM + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new boom.common.WithLargeBooms ++ // large boom config new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.system.BaseConfig) class MegaBoomConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new boom.common.WithMegaBooms ++ // 4-wide BOOM + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new boom.common.WithMegaBooms ++ // mega boom config new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.system.BaseConfig) class DualSmallBoomConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithSmallBooms ++ - new boom.common.WithNBoomCores(2) ++ // dual-core + new boom.common.WithNBoomCores(2) ++ // 2 boom cores new freechips.rocketchip.system.BaseConfig) class SmallRV32BoomConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithoutBoomFPU ++ // no fp new boom.common.WithBoomRV32 ++ // rv32 (32bit) new boom.common.WithSmallBooms ++ @@ -83,28 +127,42 @@ class SmallRV32BoomConfig extends Config( new freechips.rocketchip.system.BaseConfig) class HwachaLargeBoomConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator - new boom.common.WithLargeBooms ++ // 3-wide BOOM - new boom.common.WithNBoomCores(1) ++ - new freechips.rocketchip.system.BaseConfig) - -class LoopbackNICBoomConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithLoopbackNIC ++ // loopback the NIC - new WithIceNIC ++ // add IceNIC - new WithBootROM ++ - new WithUART ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new boom.common.WithLargeBooms ++ + new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.system.BaseConfig) + +class LoopbackNICLargeBoomConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback + new testchipip.WithTSI ++ + new icenet.WithIceNIC ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.system.BaseConfig) diff --git a/generators/chipyard/src/main/scala/ConfigMixins.scala b/generators/chipyard/src/main/scala/ConfigMixins.scala index f2dfcf2b..8234f0e3 100644 --- a/generators/chipyard/src/main/scala/ConfigMixins.scala +++ b/generators/chipyard/src/main/scala/ConfigMixins.scala @@ -1,4 +1,4 @@ -package chipyard +package chipyard.config import chisel3._ import chisel3.util.{log2Up} @@ -21,7 +21,7 @@ import hwacha.{Hwacha} import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ -import icenet.{NICKey, NICConfig} +import chipyard.{BuildTop} /** * TODO: Why do we need this? @@ -35,117 +35,40 @@ import ConfigValName._ // Common Parameter Mixins // ----------------------- -/** - * Mixin to add the Chipyard bootrom - */ class WithBootROM extends Config((site, here, up) => { case BootROMParams => BootROMParams( contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img") }) // DOC include start: gpio mixin -/** - * Mixin to add GPIOs and tie them off outside the DUT - */ class WithGPIO extends Config((site, here, up) => { case PeripheryGPIOKey => Seq( GPIOParams(address = 0x10012000, width = 4, includeIOF = false)) - case BuildTop => (clock: Clock, reset: Bool, p: Parameters, success: Bool) => { - val top = up(BuildTop, site)(clock, reset, p, success) - // TODO: Currently FIRRTL will error if the GPIO input - // pins are unconnected, so tie them to 0. - // In future IO cell blackboxes will replace this with - // more correct functionality - for (gpio <- top.gpio) { - for (pin <- gpio.pins) { - pin.i.ival := false.B - } - } - top - } }) // DOC include end: gpio mixin -/** - * Mixin to add in UART - */ class WithUART extends Config((site, here, up) => { case PeripheryUARTKey => Seq( UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256)) }) -/** - * Mixin to remove any GPIOs - */ class WithNoGPIO extends Config((site, here, up) => { case PeripheryGPIOKey => Seq() }) -// DOC include start: tsi mixin -/** - * Mixin to add an offchip TSI link (used for backing memory) - */ -class WithTSI extends Config((site, here, up) => { - case SerialKey => true - case BuildTop => (clock: Clock, reset: Bool, p: Parameters, success: Bool) => { - val top = up(BuildTop, site)(clock, reset, p, success) - success := top.connectSimSerial() - top - } -}) -// DOC include end: tsi mixin - -/** - * Mixin to add an DTM (used for dmi or jtag bringup) - */ -class WithDTM extends Config((site, here, up) => { - case BuildTop => (clock: Clock, reset: Bool, p: Parameters, success: Bool) => { - val top = up(BuildTop, site)(clock, reset, p, success) - top.reset := reset.asBool | top.debug.map { debug => AsyncResetReg(debug.ndreset) }.getOrElse(false.B) - Debug.connectDebug(top.debug, top.psd, clock, reset.asBool, success)(p) - top - } +class WithL2TLBs(entries: Int) extends Config((site, here, up) => { + case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( + core = tile.core.copy(nL2TLBEntries = entries) + )) + case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy( + core = tile.core.copy(nL2TLBEntries = entries) + )) }) -// DOC include start: GCD mixin -/** - * Mixin to add a GCD peripheral - */ -class WithGCD(useAXI4: Boolean, useBlackBox: Boolean) extends Config((site, here, up) => { - case GCDKey => Some(GCDParams(useAXI4 = useAXI4, useBlackBox = useBlackBox)) -}) -// DOC include end: GCD mixin - -/** - * Mixin to add a RTL block device model - */ -class WithBlockDeviceModel extends Config((site, here, up) => { - case BuildTop => (clock: Clock, reset: Bool, p: Parameters, success: Bool) => { - val top = up(BuildTop, site)(clock, reset, p, success) - top.connectBlockDeviceModel() - top - } +class WithTracegenTop extends Config((site, here, up) => { + case BuildTop => (p: Parameters) => Module(LazyModule(new tracegen.TraceGenSystem()(p)).suggestName("Top").module) }) -/** - * Mixin to add a simulated block device model - */ -class WithSimBlockDevice extends Config((site, here, up) => { - case BuildTop => (clock: Clock, reset: Bool, p: Parameters, success: Bool) => { - val top = up(BuildTop, site)(clock, reset, p, success) - top.connectSimBlockDevice(clock, reset) - top - } -}) - -// DOC include start: WithInitZero -/** - * Mixin to add a peripheral that clears memory - */ -class WithInitZero(base: BigInt, size: BigInt) extends Config((site, here, up) => { - case InitZeroKey => Some(InitZeroConfig(base, size)) -}) -// DOC include end: WithInitZero // ------------------ // Multi-RoCC Support @@ -215,32 +138,3 @@ class WithControlCore extends Config((site, here, up) => { ) case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1) }) - -/** - * Mixin to add an IceNIC - */ -class WithIceNIC(inBufFlits: Int = 1800, usePauser: Boolean = false) - extends Config((site, here, up) => { - case NICKey => Some(NICConfig( - inBufFlits = inBufFlits, - usePauser = usePauser, - checksumOffload = true)) -}) - -/** - * Mixin to loopback the IceNIC - */ -class WithLoopbackNIC extends Config((site, here, up) => { - case BuildTop => (clock: Clock, reset: Bool, p: Parameters, success: Bool) => { - val top = up(BuildTop, site)(clock, reset, p, success) - top.connectNicLoopback() - top - } -}) - -/** - * Mixin to add a backing scratchpad (default size 4MB) - */ -class WithBackingScratchpad(base: BigInt = 0x80000000L, mask: BigInt = ((4 << 20) - 1)) extends Config((site, here, up) => { - case BackingScratchpadKey => Some(BackingScratchpadParams(base, mask)) -}) diff --git a/generators/chipyard/src/main/scala/GCD.scala b/generators/chipyard/src/main/scala/GCD.scala index 1b66b76c..802520f0 100644 --- a/generators/chipyard/src/main/scala/GCD.scala +++ b/generators/chipyard/src/main/scala/GCD.scala @@ -1,11 +1,11 @@ -package chipyard +package chipyard.example import chisel3._ import chisel3.util._ import chisel3.experimental.{IntParam, BaseModule} import freechips.rocketchip.amba.axi4._ import freechips.rocketchip.subsystem.BaseSubsystem -import freechips.rocketchip.config.{Parameters, Field} +import freechips.rocketchip.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper.{HasRegMap, RegField} import freechips.rocketchip.tilelink._ @@ -198,3 +198,10 @@ trait CanHavePeripheryGCDModuleImp extends LazyModuleImp { } // DOC include end: GCD imp trait + + +// DOC include start: GCD mixin +class WithGCD(useAXI4: Boolean, useBlackBox: Boolean) extends Config((site, here, up) => { + case GCDKey => Some(GCDParams(useAXI4 = useAXI4, useBlackBox = useBlackBox)) +}) +// DOC include end: GCD mixin diff --git a/generators/chipyard/src/main/scala/HeteroConfigs.scala b/generators/chipyard/src/main/scala/HeteroConfigs.scala index 4bfea32c..b5cc6b8c 100644 --- a/generators/chipyard/src/main/scala/HeteroConfigs.scala +++ b/generators/chipyard/src/main/scala/HeteroConfigs.scala @@ -9,140 +9,164 @@ import freechips.rocketchip.config.{Config} // --------------------- class LargeBoomAndRocketConfig extends Config( - new WithTSI ++ // use testchipip serial offchip link - new WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) - new WithBootROM ++ // default bootrom - new WithUART ++ // add a UART - new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use SiFive l2 - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) - new boom.common.WithRenumberHarts ++ // avoid hartid overlap - new boom.common.WithLargeBooms ++ // 3-wide boom - new boom.common.WithNBoomCores(1) ++ // single-core boom - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single-core rocket - new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system - -class SmallBoomAndRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new boom.common.WithRenumberHarts ++ - new boom.common.WithSmallBooms ++ // 1-wide boom - new boom.common.WithNBoomCores(1) ++ - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter + new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts + new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) + new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing + new testchipip.WithTSI ++ // use testchipip serial offchip link + new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) + new chipyard.config.WithBootROM ++ // use default bootrom + new chipyard.config.WithUART ++ // add a UART + new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs + new boom.common.WithRenumberHarts ++ // avoid hartid overlap + new boom.common.WithLargeBooms ++ // 3-wide boom + new boom.common.WithNBoomCores(1) ++ // single-core boom + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system // DOC include start: BoomAndRocketWithHwacha class HwachaLargeBoomAndHwachaRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new hwacha.DefaultHwachaConfig ++ // add hwacha to all harts - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ new boom.common.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: BoomAndRocketWithHwacha -class RoccLargeBoomAndRoccRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithRoccExample ++ // add example rocc accelerator to all harts - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new boom.common.WithRenumberHarts ++ - new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(1) ++ - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.system.BaseConfig) - class DualLargeBoomAndRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new boom.common.WithRenumberHarts ++ + new boom.common.WithLargeBooms ++ + new boom.common.WithNBoomCores(2) ++ // 2 boom cores new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new boom.common.WithRenumberHarts ++ - new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(2) ++ // 2-boom cores + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: DualBoomAndRocketOneHwacha -class DualLargeBoomAndHwachaRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new WithMultiRoCC ++ // support heterogeneous rocc - new WithMultiRoCCHwacha(2) ++ // override: put hwacha on hart-2 (rocket) - new hwacha.DefaultHwachaConfig ++ // setup hwacha on all harts + +class LargeBoomAndHwachaRocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithMultiRoCC ++ // support heterogeneous rocc + new chipyard.config.WithMultiRoCCHwacha(1) ++ // put hwacha on hart-2 (rocket) + new chipyard.config.WithL2TLBs(1024) ++ new boom.common.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(2) ++ + new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: DualBoomAndRocketOneHwacha + + class LargeBoomAndRV32RocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new boom.common.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ - new freechips.rocketchip.subsystem.WithRV32 ++ // use 32-bit rocket + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) + // DOC include start: DualBoomAndRocket class DualLargeBoomAndDualRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new boom.common.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(2) ++ // 2 boom cores - new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 rocket cores + new boom.common.WithNBoomCores(2) ++ // 2 boom cores + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 rocket cores new freechips.rocketchip.system.BaseConfig) // DOC include end: DualBoomAndRocket -class MultiCoreWithControlCoreConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new WithControlCore ++ // add small control core (last hartid) +class LargeBoomAndRocketWithControlCoreConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithControlCore ++ // add small control core to last hartid + new chipyard.config.WithL2TLBs(1024) ++ new boom.common.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(2) ++ // 2 normal boom cores - new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 normal rocket cores + new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) + diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala new file mode 100644 index 00000000..969230b7 --- /dev/null +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -0,0 +1,131 @@ +package chipyard.iobinders + +import chisel3._ + +import freechips.rocketchip.config.{Field, Config, Parameters} +import freechips.rocketchip.diplomacy.{LazyModule} +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.system._ +import freechips.rocketchip.util._ + +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.uart._ + +import testchipip._ +import icenet._ +import tracegen.{HasTraceGenTilesModuleImp} + +import scala.reflect.{ClassTag, classTag} + +case object IOBinders extends Field[Map[String, (Clock, Bool, Bool, Any) => Seq[Any]]](Map()) + +class RegisterIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { + case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> + ((clock: Clock, reset: Bool, success: Bool, t: Any) => { + t match { + case top: T => fn(clock, reset, success, top) + case _ => Nil + } + }) + ) +}) + +class WithGPIOTiedOff extends RegisterIOBinder({ + (c, r, s, top: HasPeripheryGPIOModuleImp) => top.gpio.map(gpio => gpio.pins.map(p => p.i.ival := false.B)); Nil +}) + +class WithSimBlockDevice extends RegisterIOBinder({ + (c, r, s, top: CanHavePeripheryBlockDeviceModuleImp) => top.connectSimBlockDevice(c, r); Nil +}) + +class WithBlockDeviceModel extends RegisterIOBinder({ + (c, r, s, top: CanHavePeripheryBlockDeviceModuleImp) => top.connectBlockDeviceModel(); Nil +}) + +class WithLoopbackNIC extends RegisterIOBinder({ + (c, r, s, top: CanHavePeripheryIceNICModuleImp) => top.connectNicLoopback(); Nil +}) + +class WithUARTAdapter extends RegisterIOBinder({ + (c, r, s, top: HasPeripheryUARTModuleImp) => { + val defaultBaudRate = 115200 // matches sifive-blocks uart baudrate + top.uart.zipWithIndex.foreach{ case (dut_io, i) => + val uart_sim = Module(new UARTAdapter(i, defaultBaudRate)(top.p)) + uart_sim.io.uart.txd := dut_io.txd + dut_io.rxd := uart_sim.io.uart.rxd + } + Nil + } +}) + +class WithSimAXIMem extends RegisterIOBinder({ + (c, r, s, top: CanHaveMasterAXI4MemPortModuleImp) => top.connectSimAXIMem(); Nil +}) + +class WithSimAXIMMIO extends RegisterIOBinder({ + (c, r, s, top: CanHaveMasterAXI4MMIOPortModuleImp) => top.connectSimAXIMMIO(); Nil +}) + +class WithDontTouchPorts extends RegisterIOBinder({ + (c, r, s, top: DontTouch) => top.dontTouchPorts(); Nil +}) + +class WithTieOffInterrupts extends RegisterIOBinder({ + (c, r, s, top: HasExtInterruptsBundle) => top.tieOffInterrupts(); Nil +}) + +class WithTieOffL2FBusAXI extends RegisterIOBinder({ + (c, r, s, top: CanHaveSlaveAXI4PortModuleImp) => { + top.l2_frontend_bus_axi4.foreach(axi => { + axi.tieoff() + experimental.DataMirror.directionOf(axi.ar.ready) match { + case ActualDirection.Input => + axi.r.bits := DontCare + axi.b.bits := DontCare + case ActualDirection.Output => + axi.aw.bits := DontCare + axi.ar.bits := DontCare + axi.w.bits := DontCare + } + }) + Nil + } +}) + +class WithTiedOffDebug extends RegisterIOBinder({ + (c, r, s, top: HasPeripheryDebugModuleImp) => { + Debug.tieoffDebug(top.debug, top.psd) + // tieoffDebug doesn't actually tie everything off :/ + top.debug.foreach(_.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare })) + Nil + } +}) + +class WithSimSerial extends RegisterIOBinder({ + (c, r, s, top: CanHavePeripherySerialModuleImp) => { + val ser_success = top.connectSimSerial() + when (ser_success) { s := true.B } + Nil + } +}) + +class WithTiedOffSerial extends RegisterIOBinder({ + (c, r, s, top: CanHavePeripherySerialModuleImp) => top.tieoffSerial(); Nil +}) + + +class WithSimDTM extends RegisterIOBinder({ + (c, r, s, top: HasPeripheryDebugModuleImp) => { + val dtm_success = Wire(Bool()) + top.reset := r | top.debug.map { debug => AsyncResetReg(debug.ndreset) }.getOrElse(false.B) + Debug.connectDebug(top.debug, top.psd, c, r, dtm_success)(top.p) + when (dtm_success) { s := true.B } + Nil + } +}) + + +class WithTraceGenSuccessBinder extends RegisterIOBinder({ + (c, r, s, top: HasTraceGenTilesModuleImp) => s := top.success; Nil +}) diff --git a/generators/chipyard/src/main/scala/InitZero.scala b/generators/chipyard/src/main/scala/InitZero.scala index 2861e0bb..c351a4dd 100644 --- a/generators/chipyard/src/main/scala/InitZero.scala +++ b/generators/chipyard/src/main/scala/InitZero.scala @@ -1,9 +1,9 @@ -package chipyard +package chipyard.example import chisel3._ import chisel3.util._ import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes} -import freechips.rocketchip.config.{Parameters, Field} +import freechips.rocketchip.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange} import testchipip.TLHelper @@ -65,3 +65,10 @@ trait CanHavePeripheryInitZero { this: BaseSubsystem => fbus.fromPort(Some("init-zero"))() := initZero.node } } + + +// DOC include start: WithInitZero +class WithInitZero(base: BigInt, size: BigInt) extends Config((site, here, up) => { + case InitZeroKey => Some(InitZeroConfig(base, size)) +}) +// DOC include end: WithInitZero diff --git a/generators/chipyard/src/main/scala/NodeTypes.scala b/generators/chipyard/src/main/scala/NodeTypes.scala index ca55b2ac..0e2b6565 100644 --- a/generators/chipyard/src/main/scala/NodeTypes.scala +++ b/generators/chipyard/src/main/scala/NodeTypes.scala @@ -1,4 +1,4 @@ -package chipyard +package chipyard.example import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ diff --git a/generators/chipyard/src/main/scala/RocketConfigs.scala b/generators/chipyard/src/main/scala/RocketConfigs.scala index dfdadf03..4acf7943 100644 --- a/generators/chipyard/src/main/scala/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/RocketConfigs.scala @@ -9,233 +9,357 @@ import freechips.rocketchip.config.{Config} // -------------- class RocketConfig extends Config( - new WithTSI ++ // use testchipip serial offchip link - new WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) - new WithBootROM ++ // use default bootrom - new WithUART ++ // add a UART - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core - new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter + new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts + new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) + new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing + new testchipip.WithTSI ++ // use testchipip serial offchip link + new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) + new chipyard.config.WithBootROM ++ // use default bootrom + new chipyard.config.WithUART ++ // add a UART + new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system class HwachaRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: GemminiRocketConfig class GemminiRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new gemmini.DefaultGemminiConfig ++ // use Gemmini systolic array GEMM accelerator new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new gemmini.DefaultGemminiConfig ++ // use Gemmini systolic array GEMM accelerator + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: GemminiRocketConfig class RoccRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithRoccExample ++ // use example RoCC-based accelerator + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: JtagRocket class jtagRocketConfig extends Config( - new WithDTM ++ // use top with dtm - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithJtagDTM ++ // enable communicating with the DTM using jtag + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithSimDTM ++ // add SimJtag and SimSerial, use both to drive sim + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithJtagDTM ++ // sets DTM communication interface to JTAG new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: JtagRocket // DOC include start: DmiRocket class dmiRocketConfig extends Config( - new WithDTM ++ // use top with dtm - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffSerial ++ + new chipyard.iobinders.WithSimDTM ++ // add SimDTM and use it to drive simulation + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: DmiRocket // DOC include start: GCDTLRocketConfig class GCDTLRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithUART ++ - new WithGCD(useAXI4=false, useBlackBox=false) ++ // Use GCD Chisel, connect Tilelink - new WithBootROM ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithL2TLBs(1024) ++ + new chipyard.example.WithGCD(useAXI4=false, useBlackBox=false) ++ // Use GCD Chisel, connect Tilelink new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: GCDTLRocketConfig // DOC include start: GCDAXI4BlackBoxRocketConfig class GCDAXI4BlackBoxRocketConfig extends Config( - new WithTSI ++ - new WithUART ++ - new WithNoGPIO ++ - new WithGCD(useAXI4=true, useBlackBox=true) ++ // Use GCD blackboxed verilog, connect by AXI4->Tilelink - new WithBootROM ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithL2TLBs(1024) ++ + new chipyard.example.WithGCD(useAXI4=true, useBlackBox=true) ++ // Use GCD blackboxed verilog, connect by AXI4->Tilelink new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: GCDAXI4BlackBoxRocketConfig class SimBlockDeviceRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new chipyard.iobinders.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice + new testchipip.WithTSI ++ new testchipip.WithBlockDevice ++ // add block-device module to peripherybus - new WithSimBlockDevice ++ // use top with block-device IOs and connect to simblockdevice - new WithBootROM ++ - new WithUART ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) class BlockDeviceModelRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new chipyard.iobinders.WithBlockDeviceModel ++ // drive block-device IOs with a BlockDeviceModel + new testchipip.WithTSI ++ new testchipip.WithBlockDevice ++ // add block-device module to periphery bus - new WithBlockDeviceModel ++ // use top with block-device IOs and connect to a blockdevicemodel - new WithBootROM ++ - new WithUART ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: GPIORocketConfig class GPIORocketConfig extends Config( - new WithTSI ++ - new WithGPIO ++ // add GPIOs to the peripherybus - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new chipyard.iobinders.WithGPIOTiedOff ++ // tie off GPIO inputs into the top + new testchipip.WithTSI ++ + new chipyard.config.WithGPIO ++ // add GPIOs to the peripherybus + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: GPIORocketConfig class DualCoreRocketConfig extends Config( - new WithTSI ++ - new WithBootROM ++ - new WithUART ++ - new WithNoGPIO ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // dual-core (2 RocketTiles) new freechips.rocketchip.system.BaseConfig) class RV32RocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) class GB1MemoryRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 1GB simulated external memory new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 1GB simulated external memory + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: Sha3Rocket class Sha3RocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: Sha3Rocket // DOC include start: InitZeroRocketConfig class InitZeroRocketConfig extends Config( - new WithInitZero(0x88000000L, 0x1000L) ++ // add InitZero - new WithNoGPIO ++ - new WithTSI ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new chipyard.example.WithInitZero(0x88000000L, 0x1000L) ++ // add InitZero new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: InitZeroRocketConfig class LoopbackNICRocketConfig extends Config( - new WithTSI ++ - new WithIceNIC ++ // add an IceNIC - new WithNoGPIO ++ - new WithLoopbackNIC ++ // loopback the IceNIC - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback + new testchipip.WithTSI ++ + new icenet.WithIceNIC ++ // add an IceNIC + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) class ScratchpadRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new WithBackingScratchpad ++ // add backing scratchpad + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new testchipip.WithBackingScratchpad ++ // add backing scratchpad + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala index 6c01753f..ca861288 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -10,48 +10,21 @@ import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.util.GeneratorApp import freechips.rocketchip.devices.debug.{Debug} -/** - * TODO: Why do we need this? - */ -import ConfigValName._ +import chipyard.config.ConfigValName._ +import chipyard.iobinders.{IOBinders} // ------------------------------- // BOOM and/or Rocket Test Harness // ------------------------------- -case object BuildTop extends Field[(Clock, Bool, Parameters, Bool) => TopModule[Top]]( - (clock: Clock, reset: Bool, p: Parameters, success: Bool) => { - val top = Module(LazyModule(new Top()(p)).suggestName("top").module) - top.debug.map { debug => debug := DontCare } - top - } -) +case object BuildTop extends Field[Parameters => Any]((p: Parameters) => Module(LazyModule(new Top()(p)).suggestName("top").module)) -/** - * Test harness using TSI to bringup the system - */ class TestHarness(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val success = Output(Bool()) }) - val dut = p(BuildTop)(clock, reset.toBool, p, io.success) - dut.connectSimUARTs() - dut.connectSimAXIMem() - dut.connectSimAXIMMIO() - dut.dontTouchPorts() - dut.tieOffInterrupts() - dut.l2_frontend_bus_axi4.foreach(axi => { - axi.tieoff() - experimental.DataMirror.directionOf(axi.ar.ready) match { - case core.ActualDirection.Input => - axi.r.bits := DontCare - axi.b.bits := DontCare - case core.ActualDirection.Output => - axi.aw.bits := DontCare - axi.ar.bits := DontCare - axi.w.bits := DontCare - } - }) - + val dut = p(BuildTop)(p) + io.success := false.B + p(IOBinders).values.map(fn => fn(clock, reset.asBool, io.success, dut)) } diff --git a/generators/chipyard/src/main/scala/Top.scala b/generators/chipyard/src/main/scala/Top.scala index d4382d86..b95794e5 100644 --- a/generators/chipyard/src/main/scala/Top.scala +++ b/generators/chipyard/src/main/scala/Top.scala @@ -6,14 +6,6 @@ import freechips.rocketchip.subsystem._ import freechips.rocketchip.system._ import freechips.rocketchip.config.Parameters import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.util.DontTouch - -import testchipip._ - -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.uart._ - -import icenet.{CanHavePeripheryIceNIC, CanHavePeripheryIceNICModuleImp} // ------------------------------------ // BOOM and/or Rocket Top Level Systems @@ -21,26 +13,24 @@ import icenet.{CanHavePeripheryIceNIC, CanHavePeripheryIceNICModuleImp} // DOC include start: Top class Top(implicit p: Parameters) extends System - with CanHavePeripheryUARTAdapter // Enables optionally adding the UART print adapter - with HasPeripheryUART // Enables optionally adding the sifive UART - with HasPeripheryGPIO // Enables optionally adding the sifive GPIOs - with CanHavePeripheryBlockDevice // Enables optionally adding the block device - with CanHavePeripheryInitZero // Enables optionally adding the initzero example widget - with CanHavePeripheryGCD // Enables optionally adding the GCD example widget - with CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port - with CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim - with CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad + with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad + with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device + with testchipip.CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port + with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART + with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs + with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim + with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget + with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget { override lazy val module = new TopModule(this) } class TopModule[+L <: Top](l: L) extends SystemModule(l) - with HasPeripheryGPIOModuleImp - with HasPeripheryUARTModuleImp - with CanHavePeripheryBlockDeviceModuleImp - with CanHavePeripheryGCDModuleImp - with CanHavePeripherySerialModuleImp - with CanHavePeripheryIceNICModuleImp - with CanHavePeripheryUARTAdapterModuleImp - with DontTouch + with testchipip.CanHavePeripheryBlockDeviceModuleImp + with testchipip.CanHavePeripherySerialModuleImp + with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp + with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp + with icenet.CanHavePeripheryIceNICModuleImp + with chipyard.example.CanHavePeripheryGCDModuleImp + with freechips.rocketchip.util.DontTouch // DOC include end: Top diff --git a/generators/chipyard/src/main/scala/TopCakes.scala b/generators/chipyard/src/main/scala/TopCakes.scala deleted file mode 100644 index cd52ed55..00000000 --- a/generators/chipyard/src/main/scala/TopCakes.scala +++ /dev/null @@ -1,27 +0,0 @@ -package chipyard - -import chisel3._ - -import freechips.rocketchip.subsystem.BaseSubsystem -import freechips.rocketchip.config.{Field} -import freechips.rocketchip.diplomacy.{LazyModule, AddressSet} -import freechips.rocketchip.tilelink.{TLRAM} - -case class BackingScratchpadParams( - base: BigInt, - mask: BigInt) - -case object BackingScratchpadKey extends Field[Option[BackingScratchpadParams]](None) - -/** - * Trait to add a scratchpad on the mbus - */ -trait CanHaveBackingScratchpad { this: BaseSubsystem => - private val portName = "Backing-Scratchpad" - - val spadOpt = p(BackingScratchpadKey).map { param => - val spad = LazyModule(new TLRAM(address=AddressSet(param.base, param.mask), beatBytes=mbus.beatBytes)) - mbus.toVariableWidthSlave(Some(portName)) { spad.node } - spad - } -} diff --git a/generators/chipyard/src/main/scala/TracegenConfigs.scala b/generators/chipyard/src/main/scala/TracegenConfigs.scala new file mode 100644 index 00000000..0e3457f0 --- /dev/null +++ b/generators/chipyard/src/main/scala/TracegenConfigs.scala @@ -0,0 +1,35 @@ +package chipyard + +import chisel3._ + +import freechips.rocketchip.config.{Config} +import freechips.rocketchip.rocket.{DCacheParams} + +class TraceGenConfig extends Config( + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTraceGenSuccessBinder ++ + new chipyard.config.WithTracegenTop ++ + new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ + new freechips.rocketchip.system.BaseConfig) + +class NonBlockingTraceGenConfig extends Config( + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTraceGenSuccessBinder ++ + new chipyard.config.WithTracegenTop ++ + new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ + new freechips.rocketchip.system.BaseConfig) + +class BoomTraceGenConfig extends Config( + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTraceGenSuccessBinder ++ + new chipyard.config.WithTracegenTop ++ + new tracegen.WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ + new freechips.rocketchip.system.BaseConfig) + +class NonBlockingTraceGenL2Config extends Config( + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTraceGenSuccessBinder ++ + new chipyard.config.WithTracegenTop ++ + new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.system.BaseConfig) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index f0c9c664..2e4fbd24 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -3,52 +3,48 @@ package firesim.firesim import chisel3._ +import chisel3.experimental.annotate -import freechips.rocketchip.config.{Field, Config} +import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp} +import freechips.rocketchip.tile.{RocketTile} import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp} -import icenet.HasPeripheryIceNICModuleImpValidOnly +import icenet.CanHavePeripheryIceNICModuleImp import junctions.{NastiKey, NastiParameters} import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig} +import midas.targetutils.{MemModelAnnotation} import firesim.bridges._ import firesim.configs.MemModelKey -import firesim.util.RegisterBridgeBinder import tracegen.HasTraceGenTilesModuleImp -class WithTiedOffDebug extends RegisterBridgeBinder({ case target: HasPeripheryDebugModuleImp => - target.debug.foreach(_.clockeddmi.foreach({ cdmi => - cdmi.dmi.req.valid := false.B - cdmi.dmi.req.bits := DontCare - cdmi.dmi.resp.ready := false.B - cdmi.dmiClock := false.B.asClock - cdmi.dmiReset := false.B - })) - Seq() +import boom.common.{BoomTile} + +import chipyard.iobinders.{IOBinders, RegisterIOBinder} +import chipyard.HasBoomAndRocketTilesModuleImp + +class WithSerialBridge extends RegisterIOBinder({ + (c, r, s, target: CanHavePeripherySerialModuleImp) => target.serial.map(s => SerialBridge(s)(target.p)).toSeq }) -class WithSerialBridge extends RegisterBridgeBinder({ - case target: CanHavePeripherySerialModuleImp => Seq(SerialBridge(target.serial.get)(target.p)) +class WithNICBridge extends RegisterIOBinder({ + (c, r, s, target: CanHavePeripheryIceNICModuleImp) => target.net.map(n => NICBridge(n)(target.p)).toSeq }) -class WithNICBridge extends RegisterBridgeBinder({ - case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICBridge(target.net)(target.p)) +class WithUARTBridge extends RegisterIOBinder({ + (c, r, s, target: HasPeripheryUARTModuleImp) => target.uart.map(u => UARTBridge(u)(target.p)).toSeq }) -class WithUARTBridge extends RegisterBridgeBinder({ - case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTBridge(u)(target.p)) +class WithBlockDeviceBridge extends RegisterIOBinder({ + (c, r, s, target: CanHavePeripheryBlockDeviceModuleImp) => target.bdev.map(b => BlockDevBridge(b, target.reset.toBool)(target.p)).toSeq }) -class WithBlockDeviceBridge extends RegisterBridgeBinder({ - case target: CanHavePeripheryBlockDeviceModuleImp => Seq(BlockDevBridge(target.bdev.get, target.reset.toBool)(target.p)) -}) - -class WithFASEDBridge extends RegisterBridgeBinder({ - case t: CanHaveMasterAXI4MemPortModuleImp => +class WithFASEDBridge extends RegisterIOBinder({ + (c, r, s, t: CanHaveMasterAXI4MemPortModuleImp) => { implicit val p = t.p (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) => (io zip node.in).map({ case (axi4Bundle, (_, edge)) => @@ -59,24 +55,51 @@ class WithFASEDBridge extends RegisterBridgeBinder({ CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge)))) }) }).toSeq + } }) -class WithTracerVBridge extends RegisterBridgeBinder({ - case target: HasTraceIOImp => TracerVBridge(target.traceIO)(target.p) +class WithTracerVBridge extends RegisterIOBinder({ + (c, r, s, target: HasTraceIOImp) => Seq(TracerVBridge(target.traceIO)(target.p)) }) -class WithTraceGenBridge extends RegisterBridgeBinder({ - case target: HasTraceGenTilesModuleImp => - Seq(GroundTestBridge(target.success)(target.p)) +class WithTraceGenBridge extends RegisterIOBinder({ + (c, r, s, target: HasTraceGenTilesModuleImp) => Seq(GroundTestBridge(target.success)(target.p)) }) +class WithFireSimMultiCycleRegfile extends RegisterIOBinder({ + (c, r, s, target: HasBoomAndRocketTilesModuleImp) => { + target.outer.tiles.map { + case r: RocketTile => { + annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf)) + r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile))) + } + case b: BoomTile => { + val core = b.module.core + core.iregfile match { + case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile)) + case _ => Nil + } + if (core.fp_pipeline != null) core.fp_pipeline.fregfile match { + case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile)) + case _ => Nil + } + } + } + Nil + } +}) + + + // Shorthand to register all of the provided bridges above class WithDefaultFireSimBridges extends Config( - new WithTiedOffDebug ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithTieOffInterrupts ++ new WithSerialBridge ++ new WithNICBridge ++ new WithUARTBridge ++ new WithBlockDeviceBridge ++ new WithFASEDBridge ++ + new WithFireSimMultiCycleRegfile ++ new WithTracerVBridge ) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index b57fc305..9ecf6f48 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -2,6 +2,7 @@ package firesim.firesim import java.io.File +import chisel3._ import chisel3.util.{log2Up} import freechips.rocketchip.config.{Parameters, Config} import freechips.rocketchip.groundtest.TraceGenParams @@ -11,6 +12,7 @@ import freechips.rocketchip.rocket.DCacheParams import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey} +import freechips.rocketchip.diplomacy.LazyModule import boom.common.BoomTilesKey import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} @@ -21,6 +23,8 @@ import icenet._ import firesim.bridges._ import firesim.util.{WithNumNodes} import firesim.configs._ +import chipyard.{BuildTop} +import chipyard.config.ConfigValName._ class WithBootROM extends Config((site, here, up) => { case BootROMParams => { @@ -40,33 +44,6 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => case PeripheryBusKey => up(PeripheryBusKey).copy(frequency=freq) }) -class WithUARTKey extends Config((site, here, up) => { - case PeripheryUARTKey => List(UARTParams( - address = BigInt(0x54000000L), - nTxEntries = 256, - nRxEntries = 256)) -}) - -class WithSerial extends Config((site, here, up) => { - case SerialKey => true -}) - -class WithBlockDevice extends Config(new testchipip.WithBlockDevice) - -class WithNICKey extends Config((site, here, up) => { - case NICKey => Some(NICConfig( - inBufFlits = 8192, - ctrlQueueDepth = 64, - checksumOffload = true)) -}) - -class WithRocketL2TLBs(entries: Int) extends Config((site, here, up) => { - case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( - core = tile.core.copy( - nL2TLBEntries = entries - ) - )) -}) class WithPerfCounters extends Config((site, here, up) => { case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( @@ -74,11 +51,6 @@ class WithPerfCounters extends Config((site, here, up) => { )) }) -class WithBoomL2TLBs(entries: Int) extends Config((site, here, up) => { - case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy( - core = tile.core.copy(nL2TLBEntries = entries) - )) -}) class WithBoomEnableTrace extends Config((site, here, up) => { case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) @@ -92,7 +64,11 @@ class WithoutClockGating extends Config((site, here, up) => { // Testing configurations // This enables printfs used in testing class WithScalaTestFeatures extends Config((site, here, up) => { - case PrintTracePort => true + case PrintTracePort => true +}) + +class WithFireSimTop extends Config((site, here, up) => { + case BuildTop => (p: Parameters) => Module(LazyModule(new FireSimDUT()(p)).suggestName("top").module) }) // FASED Config Aliases. This to enable config generation via "_" concatenation @@ -114,20 +90,24 @@ class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache * determine which driver to build. *******************************************************************************/ class FireSimRocketChipConfig extends Config( - new chipyard.WithNoGPIO ++ + new chipyard.config.WithNoGPIO ++ new WithBootROM ++ new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ new WithExtMemSize(0x400000000L) ++ // 16GB new WithoutTLMonitors ++ - new WithUARTKey ++ - new WithNICKey ++ - new WithSerial ++ - new WithBlockDevice ++ - new WithRocketL2TLBs(1024) ++ + new chipyard.config.WithUART ++ + new icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) ++ + new testchipip.WithTSI ++ + new testchipip.WithBlockDevice ++ + new chipyard.config.WithL2TLBs(1024) ++ new WithPerfCounters ++ new WithoutClockGating ++ new WithDefaultMemModel ++ new WithDefaultFireSimBridges ++ + new WithFireSimTop ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.system.DefaultConfig) class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => { @@ -173,22 +153,26 @@ class FireSimRocketChipSha3L2PrintfConfig extends Config( new FireSimRocketChipConfig) class FireSimBoomConfig extends Config( - new chipyard.WithNoGPIO ++ + new chipyard.config.WithNoGPIO ++ new WithBootROM ++ new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ new WithExtMemSize(0x400000000L) ++ // 16GB new WithoutTLMonitors ++ - new WithUARTKey ++ - new WithNICKey ++ - new WithSerial ++ - new WithBlockDevice ++ new WithBoomEnableTrace ++ - new WithBoomL2TLBs(1024) ++ + new chipyard.config.WithUART ++ + new icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) ++ + new testchipip.WithTSI ++ + new testchipip.WithBlockDevice ++ + new chipyard.config.WithL2TLBs(1024) ++ new WithoutClockGating ++ new WithDefaultMemModel ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ new WithDefaultFireSimBridges ++ + new WithFireSimTop ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.system.BaseConfig ) @@ -215,10 +199,12 @@ class FireSimBoomQuadCoreConfig extends Config( // dual core config (rocket + small boom) class FireSimRocketBoomConfig extends Config( - new WithBoomL2TLBs(1024) ++ // reset l2 tlb amt ("WithSmallBooms" overrides it) + new chipyard.config.WithL2TLBs(1024) ++ // reset l2 tlb amt ("WithSmallBooms" overrides it) new boom.common.WithRenumberHarts ++ // fix hart numbering new boom.common.WithSmallBooms ++ // change single BOOM to small new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add a "big" rocket core + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ new FireSimBoomConfig ) @@ -277,72 +263,3 @@ class SupernodeFireSimRocketChipOctaCoreConfig extends Config( new WithNumNodes(4) ++ new WithExtMemSize(0x200000000L) ++ // 8GB new FireSimRocketChipOctaCoreConfig) - -class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) - extends Config((site, here, up) => { - case TraceGenKey => params.map { dcp => TraceGenParams( - dcache = Some(dcp), - wordBits = site(XLen), - addrBits = 48, - addrBag = { - val nSets = dcp.nSets - val nWays = dcp.nWays - val blockOffset = site(SystemBusKey).blockOffset - val nBeats = min(2, site(SystemBusKey).blockBeats) - val beatBytes = site(SystemBusKey).beatBytes - List.tabulate(2 * nWays) { i => - Seq.tabulate(nBeats) { j => - BigInt((j * beatBytes) + ((i * nSets) << blockOffset)) - } - }.flatten - }, - maxRequests = nReqs, - memStart = site(ExtMem).get.master.base, - numGens = params.size) - } - case MaxHartIdBits => log2Up(params.size) -}) - -class FireSimTraceGenConfig extends Config( - new WithTraceGen( - List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ - new WithTraceGenBridge ++ - new FireSimRocketChipConfig) - -class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) - extends Config((site, here, up) => { - case TraceGenKey => params.map { dcp => TraceGenParams( - dcache = Some(dcp), - wordBits = site(XLen), - addrBits = 48, - addrBag = { - val sbp = site(SystemBusKey) - val l2p = site(InclusiveCacheKey) - val nSets = max(l2p.sets, dcp.nSets) - val nWays = max(l2p.ways, dcp.nWays) - val nBanks = site(BankedL2Key).nBanks - val blockOffset = sbp.blockOffset - val nBeats = min(2, sbp.blockBeats) - val beatBytes = sbp.beatBytes - List.tabulate(2 * nWays) { i => - Seq.tabulate(nBeats) { j => - BigInt((j * beatBytes) + ((i * nSets * nBanks) << blockOffset)) - } - }.flatten - }, - maxRequests = nReqs, - memStart = site(ExtMem).get.master.base, - numGens = params.size) - } - case MaxHartIdBits => log2Up(params.size) -}) - -class FireSimTraceGenL2Config extends Config( - new WithL2TraceGen( - List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ - new WithInclusiveCache( - nBanks = 4, - capacityKB = 1024, - outerLatencyCycles = 50) ++ - new WithTraceGenBridge ++ - new FireSimRocketChipConfig) diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetTraits.scala similarity index 100% rename from generators/firechip/src/main/scala/TargetMixins.scala rename to generators/firechip/src/main/scala/TargetTraits.scala diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index ecb6665c..bdbda075 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -26,6 +26,8 @@ object FireSimValName { } import FireSimValName._ + + /******************************************************************************* * Top level DESIGN configurations. These describe the basic instantiations of * the designs being simulated. @@ -44,40 +46,23 @@ class FireSimDUT(implicit p: Parameters) extends chipyard.Top } class FireSimModuleImp[+L <: FireSimDUT](l: L) extends chipyard.TopModule(l) - with HasTraceIOImp - with CanHaveMultiCycleRegfileImp + with HasTraceIOImp + with CanHaveMultiCycleRegfileImp -class FireSim(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT) +class FireSim(implicit p: Parameters) extends DefaultFireSimHarness -// Kept for legacy-reasons, this is equivalent to FireSimDUT -class FireSimNoNICDUT(implicit p: Parameters) extends FireSimDUT -class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimNoNICDUT) - -class FireSimTraceGenDUT(implicit p: Parameters) extends BaseSubsystem - with HasHierarchicalBusTopology - with HasTraceGenTiles - with CanHaveMasterAXI4MemPort { - override lazy val module = new FireSimTraceGenModuleImp(this) -} - -class FireSimTraceGenModuleImp(outer: FireSimTraceGenDUT) extends BaseSubsystemModuleImp(outer) - with HasTraceGenTilesModuleImp - with CanHaveMasterAXI4MemPortModuleImp - -class FireSimTraceGen(implicit p: Parameters) extends DefaultFireSimHarness( - () => new FireSimTraceGenDUT) - -// Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimHarness) to something > 1 -class FireSimSupernode(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT) - -// Verilog blackbox integration demo -class FireSimVerilogGCDDUT(implicit p: Parameters) extends FireSimDUT - with chipyard.CanHavePeripheryGCD +class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness { - override lazy val module = new FireSimVerilogGCDModuleImp(this) + throw new Exception("FireSimNoNIC is deprecated. Please add WithNoNIC to your TARGET_CONFIG and set DESIGN=FireSim to build a NoNIC simulator") } -class FireSimVerilogGCDModuleImp[+L <: FireSimVerilogGCDDUT](l: L) extends FireSimModuleImp(l) -class FireSimVerilogGCD(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimVerilogGCDDUT) +object FireSimTypeAliases { + // Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimHarness) to something > 1 + type FireSimSupernode = FireSim + + // Verilog blackbox integration demo + type FireSimVerilogGCD = FireSim +} +import FireSimTypeAliases._ diff --git a/generators/icenet b/generators/icenet index 49b6dfb6..4980d3a3 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 49b6dfb6341bf128e95c549e42f881ad16dd45a5 +Subproject commit 4980d3a311e487419f2e6358d678c18b7ff3ffe4 diff --git a/generators/testchipip b/generators/testchipip index c11549ba..ff1daef0 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit c11549ba30483ee3c0d331fb893c45814bdb6b63 +Subproject commit ff1daef09f2f9c2fdea5e93a3b38c58a226b7b3c diff --git a/generators/tracegen/src/main/scala/Configs.scala b/generators/tracegen/src/main/scala/Configs.scala index dd195296..c22b0e3d 100644 --- a/generators/tracegen/src/main/scala/Configs.scala +++ b/generators/tracegen/src/main/scala/Configs.scala @@ -60,19 +60,6 @@ class WithBoomTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) case MaxHartIdBits => log2Ceil(params.size + up(TraceGenKey, site).length) max 1 }) - -class TraceGenConfig extends Config( - new WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ - new BaseConfig) - -class NonBlockingTraceGenConfig extends Config( - new WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ - new BaseConfig) - -class BoomTraceGenConfig extends Config( - new WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ - new BaseConfig) - class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) extends Config((site, here, up) => { case TraceGenKey => params.map { dcp => TraceGenParams( @@ -100,7 +87,3 @@ class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) case MaxHartIdBits => if (params.size == 1) 1 else log2Ceil(params.size) }) -class NonBlockingTraceGenL2Config extends Config( - new WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ - new WithInclusiveCache ++ - new BaseConfig) diff --git a/generators/tracegen/src/main/scala/TestHarness.scala b/generators/tracegen/src/main/scala/TestHarness.scala deleted file mode 100644 index 5e07909f..00000000 --- a/generators/tracegen/src/main/scala/TestHarness.scala +++ /dev/null @@ -1,27 +0,0 @@ -package tracegen - -import chisel3._ -import freechips.rocketchip.config.Parameters -import freechips.rocketchip.diplomacy.LazyModule -import freechips.rocketchip.util.GeneratorApp - -class TestHarness(implicit p: Parameters) extends Module { - val io = IO(new Bundle { - val success = Output(Bool()) - }) - - val dut = Module(LazyModule(new TraceGenSystem).module) - io.success := dut.success - dut.connectSimAXIMem() -} - -object Generator extends GeneratorApp { - // specify the name that the generator outputs files as - override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs - - // generate files - generateFirrtl - generateAnno - generateTestSuiteMakefrags - generateArtefacts -} diff --git a/sims/firesim b/sims/firesim index 52aee63b..c771d114 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 52aee63bc04c3769695a41ba18319e316c2e78d5 +Subproject commit c771d1143a98dd19f1c4a842cc8a572b5e54de98 diff --git a/variables.mk b/variables.mk index 1ddada7b..d124fed6 100644 --- a/variables.mk +++ b/variables.mk @@ -38,17 +38,6 @@ ifeq ($(SUB_PROJECT),chipyard) TB ?= TestDriver TOP ?= Top endif -ifeq ($(SUB_PROJECT),tracegen) - SBT_PROJECT ?= tracegen - MODEL ?= TestHarness - VLOG_MODEL ?= $(MODEL) - MODEL_PACKAGE ?= $(SBT_PROJECT) - CONFIG ?= TraceGenConfig - CONFIG_PACKAGE ?= $(SBT_PROJECT) - GENERATOR_PACKAGE ?= $(SBT_PROJECT) - TB ?= TestDriver - TOP ?= TraceGenSystem -endif # for Rocket-chip developers ifeq ($(SUB_PROJECT),rocketchip) SBT_PROJECT ?= rocketchip