Generator unification
This commit is contained in:
Jerry Zhao
@@ -2,6 +2,7 @@ package firesim.firesim
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import java.io.File
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import chisel3._
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import chisel3.util.{log2Up}
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import freechips.rocketchip.config.{Parameters, Config}
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import freechips.rocketchip.groundtest.TraceGenParams
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@@ -11,6 +12,7 @@ import freechips.rocketchip.rocket.DCacheParams
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.devices.tilelink.BootROMParams
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import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
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import freechips.rocketchip.diplomacy.LazyModule
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import boom.common.BoomTilesKey
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import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey}
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import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
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@@ -21,6 +23,8 @@ import icenet._
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import firesim.bridges._
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import firesim.util.{WithNumNodes}
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import firesim.configs._
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import chipyard.{BuildTop}
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import chipyard.config.ConfigValName._
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class WithBootROM extends Config((site, here, up) => {
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case BootROMParams => {
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@@ -40,33 +44,6 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) =>
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case PeripheryBusKey => up(PeripheryBusKey).copy(frequency=freq)
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})
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class WithUARTKey extends Config((site, here, up) => {
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case PeripheryUARTKey => List(UARTParams(
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address = BigInt(0x54000000L),
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nTxEntries = 256,
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nRxEntries = 256))
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})
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class WithSerial extends Config((site, here, up) => {
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case SerialKey => true
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})
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class WithBlockDevice extends Config(new testchipip.WithBlockDevice)
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class WithNICKey extends Config((site, here, up) => {
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case NICKey => Some(NICConfig(
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inBufFlits = 8192,
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ctrlQueueDepth = 64,
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checksumOffload = true))
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})
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class WithRocketL2TLBs(entries: Int) extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy(
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core = tile.core.copy(
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nL2TLBEntries = entries
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)
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))
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})
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class WithPerfCounters extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy(
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@@ -74,11 +51,6 @@ class WithPerfCounters extends Config((site, here, up) => {
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))
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})
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class WithBoomL2TLBs(entries: Int) extends Config((site, here, up) => {
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case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(
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core = tile.core.copy(nL2TLBEntries = entries)
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))
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})
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class WithBoomEnableTrace extends Config((site, here, up) => {
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case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
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@@ -92,7 +64,11 @@ class WithoutClockGating extends Config((site, here, up) => {
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// Testing configurations
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// This enables printfs used in testing
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class WithScalaTestFeatures extends Config((site, here, up) => {
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case PrintTracePort => true
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case PrintTracePort => true
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})
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class WithFireSimTop extends Config((site, here, up) => {
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case BuildTop => (p: Parameters) => Module(LazyModule(new FireSimDUT()(p)).suggestName("top").module)
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})
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// FASED Config Aliases. This to enable config generation via "_" concatenation
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@@ -114,20 +90,24 @@ class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache
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* determine which driver to build.
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*******************************************************************************/
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class FireSimRocketChipConfig extends Config(
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new chipyard.WithNoGPIO ++
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new chipyard.config.WithNoGPIO ++
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new WithBootROM ++
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new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
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new WithExtMemSize(0x400000000L) ++ // 16GB
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new WithoutTLMonitors ++
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new WithUARTKey ++
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new WithNICKey ++
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new WithSerial ++
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new WithBlockDevice ++
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new WithRocketL2TLBs(1024) ++
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new chipyard.config.WithUART ++
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new icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) ++
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new testchipip.WithTSI ++
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new testchipip.WithBlockDevice ++
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new chipyard.config.WithL2TLBs(1024) ++
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new WithPerfCounters ++
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new WithoutClockGating ++
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new WithDefaultMemModel ++
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new WithDefaultFireSimBridges ++
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new WithFireSimTop ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.system.DefaultConfig)
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class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => {
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@@ -173,22 +153,26 @@ class FireSimRocketChipSha3L2PrintfConfig extends Config(
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new FireSimRocketChipConfig)
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class FireSimBoomConfig extends Config(
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new chipyard.WithNoGPIO ++
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new chipyard.config.WithNoGPIO ++
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new WithBootROM ++
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new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
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new WithExtMemSize(0x400000000L) ++ // 16GB
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new WithoutTLMonitors ++
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new WithUARTKey ++
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new WithNICKey ++
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new WithSerial ++
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new WithBlockDevice ++
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new WithBoomEnableTrace ++
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new WithBoomL2TLBs(1024) ++
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new chipyard.config.WithUART ++
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new icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) ++
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new testchipip.WithTSI ++
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new testchipip.WithBlockDevice ++
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new chipyard.config.WithL2TLBs(1024) ++
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new WithoutClockGating ++
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new WithDefaultMemModel ++
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new boom.common.WithLargeBooms ++
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new boom.common.WithNBoomCores(1) ++
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new WithDefaultFireSimBridges ++
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new WithFireSimTop ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.system.BaseConfig
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)
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@@ -215,10 +199,12 @@ class FireSimBoomQuadCoreConfig extends Config(
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// dual core config (rocket + small boom)
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class FireSimRocketBoomConfig extends Config(
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new WithBoomL2TLBs(1024) ++ // reset l2 tlb amt ("WithSmallBooms" overrides it)
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new chipyard.config.WithL2TLBs(1024) ++ // reset l2 tlb amt ("WithSmallBooms" overrides it)
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new boom.common.WithRenumberHarts ++ // fix hart numbering
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new boom.common.WithSmallBooms ++ // change single BOOM to small
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add a "big" rocket core
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new FireSimBoomConfig
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)
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@@ -277,72 +263,3 @@ class SupernodeFireSimRocketChipOctaCoreConfig extends Config(
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new WithNumNodes(4) ++
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new WithExtMemSize(0x200000000L) ++ // 8GB
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new FireSimRocketChipOctaCoreConfig)
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class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
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extends Config((site, here, up) => {
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case TraceGenKey => params.map { dcp => TraceGenParams(
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dcache = Some(dcp),
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wordBits = site(XLen),
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addrBits = 48,
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addrBag = {
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val nSets = dcp.nSets
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val nWays = dcp.nWays
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val blockOffset = site(SystemBusKey).blockOffset
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val nBeats = min(2, site(SystemBusKey).blockBeats)
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val beatBytes = site(SystemBusKey).beatBytes
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List.tabulate(2 * nWays) { i =>
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Seq.tabulate(nBeats) { j =>
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BigInt((j * beatBytes) + ((i * nSets) << blockOffset))
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}
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}.flatten
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},
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maxRequests = nReqs,
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memStart = site(ExtMem).get.master.base,
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numGens = params.size)
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}
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case MaxHartIdBits => log2Up(params.size)
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})
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class FireSimTraceGenConfig extends Config(
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new WithTraceGen(
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List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
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new WithTraceGenBridge ++
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new FireSimRocketChipConfig)
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class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
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extends Config((site, here, up) => {
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case TraceGenKey => params.map { dcp => TraceGenParams(
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dcache = Some(dcp),
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wordBits = site(XLen),
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addrBits = 48,
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addrBag = {
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val sbp = site(SystemBusKey)
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val l2p = site(InclusiveCacheKey)
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val nSets = max(l2p.sets, dcp.nSets)
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val nWays = max(l2p.ways, dcp.nWays)
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val nBanks = site(BankedL2Key).nBanks
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val blockOffset = sbp.blockOffset
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val nBeats = min(2, sbp.blockBeats)
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val beatBytes = sbp.beatBytes
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List.tabulate(2 * nWays) { i =>
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Seq.tabulate(nBeats) { j =>
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BigInt((j * beatBytes) + ((i * nSets * nBanks) << blockOffset))
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}
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}.flatten
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},
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maxRequests = nReqs,
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memStart = site(ExtMem).get.master.base,
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numGens = params.size)
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}
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case MaxHartIdBits => log2Up(params.size)
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})
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class FireSimTraceGenL2Config extends Config(
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new WithL2TraceGen(
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List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
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new WithInclusiveCache(
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nBanks = 4,
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capacityKB = 1024,
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outerLatencyCycles = 50) ++
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new WithTraceGenBridge ++
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new FireSimRocketChipConfig)
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