Generator unification

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -3,52 +3,48 @@
 package firesim.firesim
 
 import chisel3._
+import chisel3.experimental.annotate
 
-import freechips.rocketchip.config.{Field, Config}
+import freechips.rocketchip.config.{Field, Config, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule}
 import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp
 import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp}
+import freechips.rocketchip.tile.{RocketTile}
 import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
 
 import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp}
-import icenet.HasPeripheryIceNICModuleImpValidOnly
+import icenet.CanHavePeripheryIceNICModuleImp
 
 import junctions.{NastiKey, NastiParameters}
 import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig}
+import midas.targetutils.{MemModelAnnotation}
 import firesim.bridges._
 import firesim.configs.MemModelKey
-import firesim.util.RegisterBridgeBinder
 import tracegen.HasTraceGenTilesModuleImp
 
-class WithTiedOffDebug extends RegisterBridgeBinder({ case target: HasPeripheryDebugModuleImp =>
-  target.debug.foreach(_.clockeddmi.foreach({ cdmi =>
-    cdmi.dmi.req.valid := false.B
-    cdmi.dmi.req.bits := DontCare
-    cdmi.dmi.resp.ready := false.B
-    cdmi.dmiClock := false.B.asClock
-    cdmi.dmiReset := false.B
-  }))
-  Seq()
+import boom.common.{BoomTile}
+
+import chipyard.iobinders.{IOBinders, RegisterIOBinder}
+import chipyard.HasBoomAndRocketTilesModuleImp
+
+class WithSerialBridge extends RegisterIOBinder({
+  (c, r, s, target: CanHavePeripherySerialModuleImp) => target.serial.map(s => SerialBridge(s)(target.p)).toSeq
 })
 
-class WithSerialBridge extends RegisterBridgeBinder({
-  case target: CanHavePeripherySerialModuleImp => Seq(SerialBridge(target.serial.get)(target.p))
+class WithNICBridge extends RegisterIOBinder({
+  (c, r, s, target: CanHavePeripheryIceNICModuleImp) => target.net.map(n => NICBridge(n)(target.p)).toSeq
 })
 
-class WithNICBridge extends RegisterBridgeBinder({
-  case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICBridge(target.net)(target.p))
+class WithUARTBridge extends RegisterIOBinder({
+  (c, r, s, target: HasPeripheryUARTModuleImp) => target.uart.map(u => UARTBridge(u)(target.p)).toSeq
 })
 
-class WithUARTBridge extends RegisterBridgeBinder({
-  case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTBridge(u)(target.p))
+class WithBlockDeviceBridge extends RegisterIOBinder({
+  (c, r, s, target: CanHavePeripheryBlockDeviceModuleImp) => target.bdev.map(b => BlockDevBridge(b, target.reset.toBool)(target.p)).toSeq
 })
 
-class WithBlockDeviceBridge extends RegisterBridgeBinder({
-  case target: CanHavePeripheryBlockDeviceModuleImp => Seq(BlockDevBridge(target.bdev.get, target.reset.toBool)(target.p))
-})
-
-class WithFASEDBridge extends RegisterBridgeBinder({
-  case t: CanHaveMasterAXI4MemPortModuleImp =>
+class WithFASEDBridge extends RegisterIOBinder({
+  (c, r, s, t: CanHaveMasterAXI4MemPortModuleImp) => {
     implicit val p = t.p
     (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) =>
       (io zip node.in).map({ case (axi4Bundle, (_, edge)) =>
@@ -59,24 +55,51 @@ class WithFASEDBridge extends RegisterBridgeBinder({
           CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge))))
       })
     }).toSeq
+  }
 })
 
-class WithTracerVBridge extends RegisterBridgeBinder({
-  case target: HasTraceIOImp => TracerVBridge(target.traceIO)(target.p)
+class WithTracerVBridge extends RegisterIOBinder({
+  (c, r, s, target: HasTraceIOImp) => Seq(TracerVBridge(target.traceIO)(target.p))
 })
 
-class WithTraceGenBridge extends RegisterBridgeBinder({
-  case target: HasTraceGenTilesModuleImp =>
-    Seq(GroundTestBridge(target.success)(target.p))
+class WithTraceGenBridge extends RegisterIOBinder({
+  (c, r, s, target: HasTraceGenTilesModuleImp) => Seq(GroundTestBridge(target.success)(target.p))
 })
 
+class WithFireSimMultiCycleRegfile extends RegisterIOBinder({
+  (c, r, s, target: HasBoomAndRocketTilesModuleImp) => {
+    target.outer.tiles.map {
+      case r: RocketTile => {
+        annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf))
+        r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))
+      }
+      case b: BoomTile => {
+        val core = b.module.core
+        core.iregfile match {
+          case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
+          case _ => Nil
+        }
+        if (core.fp_pipeline != null) core.fp_pipeline.fregfile match {
+          case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile))
+          case _ => Nil
+        }
+      }
+    }
+    Nil
+  }
+})
+
+
+
 // Shorthand to register all of the provided bridges above
 class WithDefaultFireSimBridges extends Config(
-  new WithTiedOffDebug ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
   new WithSerialBridge ++
   new WithNICBridge ++
   new WithUARTBridge ++
   new WithBlockDeviceBridge ++
   new WithFASEDBridge ++
+  new WithFireSimMultiCycleRegfile ++
   new WithTracerVBridge
 )