35 lines
944 B
Scala
35 lines
944 B
Scala
package chipyard.fpga.arty
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import chisel3._
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import freechips.rocketchip.diplomacy.{LazyModule}
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import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters}
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import org.chipsalliance.cde.config.{Parameters}
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import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
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import chipyard.harness.{HasHarnessInstantiators}
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class Arty35THarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessInstantiators {
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// Convert harness resets from Bool to Reset type.
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val hReset = Wire(Reset())
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hReset := ~ck_rst
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val dReset = Wire(AsyncReset())
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dReset := reset_core.asAsyncReset
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def success = {require(false, "Success not supported"); false.B }
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def referenceClockFreqMHz = 32.0
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def referenceClock = clock_32MHz
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def referenceReset = hReset
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dut_jtag_TCK := DontCare
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dut_jtag_TMS := DontCare
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dut_jtag_TDI := DontCare
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dut_jtag_TDO := DontCare
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dut_jtag_reset := DontCare
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instantiateChipTops()
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}
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