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adding more Memtrace configs of different Sbus width

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This commit is contained in:
Vamber Yang
2023-05-16 05:54:16 -07:00
parent 7ed3d294c8
commit e7980b7b75
1 changed files with 36 additions and 0 deletions
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36
generators/chipyard/src/main/scala/config/GPUConfig.scala
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@@ -3,6 +3,7 @@ package chipyard
import org.chipsalliance.cde.config.{Config} import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing} import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
class MemtraceCoreConfig extends Config( class MemtraceCoreConfig extends Config(
// Memtrace // Memtrace
new freechips.rocketchip.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace", new freechips.rocketchip.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace",
@@ -19,3 +20,38 @@ class MemtraceCoreConfig extends Config(
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++ new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new chipyard.config.AbstractConfig new chipyard.config.AbstractConfig
) )
class MemtraceCore128SbusConfig extends Config(
// Memtrace
new freechips.rocketchip.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace",
traceHasSource = false) ++
// new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
// traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer ++
new freechips.rocketchip.subsystem.WithNLanes(4) ++
// L2
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(128) ++
// Small Rocket core that does nothing
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new chipyard.config.AbstractConfig
)
class MemtraceCore256SbusConfig extends Config(
// Memtrace
new freechips.rocketchip.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace",
traceHasSource = false) ++
// new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
// traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer ++
new freechips.rocketchip.subsystem.WithNLanes(4) ++
// L2
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(256) ++
// Small Rocket core that does nothing
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new chipyard.config.AbstractConfig
)