diff --git a/generators/chipyard/src/main/scala/config/GPUConfig.scala b/generators/chipyard/src/main/scala/config/GPUConfig.scala
index 11ae3241..5282100c 100644
--- a/generators/chipyard/src/main/scala/config/GPUConfig.scala
+++ b/generators/chipyard/src/main/scala/config/GPUConfig.scala
@@ -3,6 +3,7 @@ package chipyard
 import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 
+
 class MemtraceCoreConfig extends Config(
   // Memtrace
   new freechips.rocketchip.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace",
@@ -19,3 +20,38 @@ class MemtraceCoreConfig extends Config(
   new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
   new chipyard.config.AbstractConfig
   )
+
+
+class MemtraceCore128SbusConfig extends Config(
+  // Memtrace
+  new freechips.rocketchip.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace",
+    traceHasSource = false) ++
+  // new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
+  //   traceHasSource = false) ++
+  new freechips.rocketchip.subsystem.WithCoalescer ++
+  new freechips.rocketchip.subsystem.WithNLanes(4) ++
+  // L2
+  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
+  new freechips.rocketchip.subsystem.WithNBanks(4) ++                                   
+  new chipyard.config.WithSystemBusWidth(128) ++ 
+  // Small Rocket core that does nothing
+  new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
+  new chipyard.config.AbstractConfig
+)
+
+class MemtraceCore256SbusConfig extends Config(
+  // Memtrace
+  new freechips.rocketchip.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace",
+    traceHasSource = false) ++
+  // new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
+  //   traceHasSource = false) ++
+  new freechips.rocketchip.subsystem.WithCoalescer ++
+  new freechips.rocketchip.subsystem.WithNLanes(4) ++
+  // L2
+  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
+  new freechips.rocketchip.subsystem.WithNBanks(4) ++                                   
+  new chipyard.config.WithSystemBusWidth(256) ++ 
+  // Small Rocket core that does nothing
+  new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
+  new chipyard.config.AbstractConfig
+)
\ No newline at end of file