Add WithCoalescer to SoC config
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@@ -6,7 +6,10 @@ import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
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class MemtraceCoreConfig extends Config(
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// Memtrace
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new freechips.rocketchip.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace",
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traceHasSource = true) ++
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traceHasSource = false) ++
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// new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
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// traceHasSource = false) ++
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new freechips.rocketchip.subsystem.WithCoalescer ++
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new freechips.rocketchip.subsystem.WithNLanes(4) ++
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// L2
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new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
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Submodule generators/rocket-chip updated: 640a58b7a9...23b5ad37e4
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