diff --git a/Makefrag b/Makefrag index 3d36b3cb..ab993500 100644 --- a/Makefrag +++ b/Makefrag @@ -8,7 +8,7 @@ SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch lookup_scala_srcs = $(shell find $(1)/ -iname "*.scala" 2> /dev/null) -PACKAGES=rocket-chip testchipip +PACKAGES=rocket-chip testchipip barstools SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/src/main/scala) ROCKET_CLASSES ?= "$(ROCKETCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-$(SCALA_VERSION_MAJOR)/*" @@ -25,7 +25,11 @@ build_dir=$(sim_dir)/generated-src CHISEL_ARGS ?= +ifneq ($(PROJECT),example) +long_name=$(PROJECT).$(CONFIG) +else long_name=$(PROJECT).$(MODEL).$(CONFIG) +endif FIRRTL_FILE ?=$(build_dir)/$(long_name).fir ANNO_FILE ?=$(build_dir)/$(long_name).anno.json @@ -35,6 +39,9 @@ TOP_ANNO ?=$(build_dir)/$(long_name).top.anno.json HARNESS_FILE ?=$(build_dir)/$(long_name).harness.v HARNESS_FIR ?=$(build_dir)/$(long_name).harness.fir HARNESS_ANNO ?=$(build_dir)/$(long_name).harness.anno.json +HARNESS_SMEMS_FILE ?=$(build_dir)/$(long_name).harness.mems.v +HARNESS_SMEMS_CONF ?=$(build_dir)/$(long_name).harness.mems.conf +HARNESS_SMEMS_FIR ?=$(build_dir)/$(long_name).harness.mems.fir SMEMS_FILE ?=$(build_dir)/$(long_name).mems.v SMEMS_CONF ?=$(build_dir)/$(long_name).mems.conf SMEMS_FIR ?=$(build_dir)/$(long_name).mems.fir @@ -43,6 +50,7 @@ sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF) +HARNESS_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(HARNESS_SMEMS_CONF) $(sim_dotf): $(SCALA_SOURCES) $(FIRRTL_JAR) cd $(base_dir) && $(SBT) "runMain example.GenerateSimFiles -td $(build_dir) -sim $(sim_name)" @@ -56,7 +64,7 @@ $(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FI cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes) $(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes) - cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) -td $(build_dir)" + cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) $(HARNESS_REPL_SEQ_MEM) -td $(build_dir)" grep -v "SimSerial.cc\|SimDTM.cc\|SimJTAG.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes) # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs @@ -64,6 +72,10 @@ MACROCOMPILER_MODE ?= --mode synflops $(SMEMS_FILE) $(SMEMS_FIR): $(SMEMS_CONF) cd $(base_dir) && $(SBT) "project barstools-macros" "runMain barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) -f $(SMEMS_FIR) $(MACROCOMPILER_MODE)" +HARNESS_MACROCOMPILER_MODE = --mode synflops +$(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): $(HARNESS_SMEMS_CONF) + cd $(base_dir) && $(SBT) "project barstools-macros" "runMain barstools.macros.MacroCompiler -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)" + regression-tests = \ rv64ud-v-fcvt \ rv64ud-p-fdiv \ diff --git a/barstools b/barstools index e548210e..7d3c3337 160000 --- a/barstools +++ b/barstools @@ -1 +1 @@ -Subproject commit e548210ef42e634e75cf283292685728114694c6 +Subproject commit 7d3c333765920ef9175c3d0eee6a6326f5e09a18 diff --git a/rocket-chip b/rocket-chip index a05728c4..b8baef6f 160000 --- a/rocket-chip +++ b/rocket-chip @@ -1 +1 @@ -Subproject commit a05728c4fab84a13585e14ac684b47c875b17b57 +Subproject commit b8baef6f26fa36c9b4e0b2a5eec12cd76ae5daf8 diff --git a/src/main/scala/example/Configs.scala b/src/main/scala/example/Configs.scala index b7664614..3b009704 100644 --- a/src/main/scala/example/Configs.scala +++ b/src/main/scala/example/Configs.scala @@ -2,7 +2,7 @@ package example import chisel3._ import freechips.rocketchip.config.{Parameters, Config} -import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} +import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize} import freechips.rocketchip.diplomacy.{LazyModule, ValName} import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.tile.XLen @@ -76,6 +76,19 @@ class WithFourTrackers extends WithNBlockDeviceTrackers(4) class WithTwoMemChannels extends WithNMemoryChannels(2) class WithFourMemChannels extends WithNMemoryChannels(4) +// 16GB of off chip memory +class BigMemoryConfig extends Config( + new WithExtMemSize((1<<30) * 16L) ++ new DefaultExampleConfig) +// 1GB of off chip memory +class GB1MemoryConfig extends Config( + new WithExtMemSize((1<<30) * 1L) ++ new DefaultExampleConfig) +class GB2MemoryConfig extends Config( + new WithExtMemSize((1<<30) * 2L) ++ new DefaultExampleConfig) +class GB4MemoryConfig extends Config( + new WithExtMemSize((1<<30) * 4L) ++ new DefaultExampleConfig) +class GB8MemoryConfig extends Config( + new WithExtMemSize((1<<30) * 8L) ++ new DefaultExampleConfig) + class DualCoreConfig extends Config( // Core gets tacked onto existing list new WithNBigCores(2) ++ new DefaultExampleConfig) diff --git a/src/main/scala/example/TestHarness.scala b/src/main/scala/example/TestHarness.scala index a5af6240..2fcc42c4 100644 --- a/src/main/scala/example/TestHarness.scala +++ b/src/main/scala/example/TestHarness.scala @@ -6,6 +6,10 @@ import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper} import freechips.rocketchip.diplomacy.LazyModule import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.util.GeneratorApp +import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite} +import freechips.rocketchip.subsystem.RocketTilesKey +import freechips.rocketchip.tile.XLen +import scala.collection.mutable.LinkedHashSet case object BuildTop extends Field[(Clock, Bool, Parameters) => ExampleTopModule[ExampleTop]] @@ -36,6 +40,82 @@ class TestHarness(implicit val p: Parameters) extends Module { } object Generator extends GeneratorApp { + //Copied from rocketchip + val rv64RegrTestNames = LinkedHashSet( + "rv64ud-v-fcvt", + "rv64ud-p-fdiv", + "rv64ud-v-fadd", + "rv64uf-v-fadd", + "rv64um-v-mul", + "rv64mi-p-breakpoint", + "rv64uc-v-rvc", + "rv64ud-v-structural", + "rv64si-p-wfi", + "rv64um-v-divw", + "rv64ua-v-lrsc", + "rv64ui-v-fence_i", + "rv64ud-v-fcvt_w", + "rv64uf-v-fmin", + "rv64ui-v-sb", + "rv64ua-v-amomax_d", + "rv64ud-v-move", + "rv64ud-v-fclass", + "rv64ua-v-amoand_d", + "rv64ua-v-amoxor_d", + "rv64si-p-sbreak", + "rv64ud-v-fmadd", + "rv64uf-v-ldst", + "rv64um-v-mulh", + "rv64si-p-dirty") + + val rv32RegrTestNames = LinkedHashSet( + "rv32mi-p-ma_addr", + "rv32mi-p-csr", + "rv32ui-p-sh", + "rv32ui-p-lh", + "rv32uc-p-rvc", + "rv32mi-p-sbreak", + "rv32ui-p-sll") + + + override def addTestSuites { + import freechips.rocketchip.system.DefaultTestSuites._ + val xlen = params(XLen) + // TODO: for now only generate tests for the first core in the first subsystem + params(RocketTilesKey).headOption.map { tileParams => + val coreParams = tileParams.core + val vm = coreParams.useVM + val env = if (vm) List("p","v") else List("p") + coreParams.fpu foreach { case cfg => + if (xlen == 32) { + TestGeneration.addSuites(env.map(rv32uf)) + if (cfg.fLen >= 64) + TestGeneration.addSuites(env.map(rv32ud)) + } else { + TestGeneration.addSuite(rv32udBenchmarks) + TestGeneration.addSuites(env.map(rv64uf)) + if (cfg.fLen >= 64) + TestGeneration.addSuites(env.map(rv64ud)) + } + } + if (coreParams.useAtomics) { + if (tileParams.dcache.flatMap(_.scratch).isEmpty) + TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + else + TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + } + if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + val (rvi, rvu) = + if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) + else ((if (vm) rv32i else rv32pi), rv32u) + + TestGeneration.addSuites(rvi.map(_("p"))) + TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) + TestGeneration.addSuite(benchmarks) + TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + } + } + //End copied from rocketchip val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs generateFirrtl generateAnno diff --git a/verisim/Makefile b/verisim/Makefile index dbc5ee28..f181f32b 100644 --- a/verisim/Makefile +++ b/verisim/Makefile @@ -31,6 +31,7 @@ rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc sim_vsrcs = \ $(VERILOG_FILE) \ $(HARNESS_FILE) \ + $(HARNESS_SMEMS_FILE) \ $(SMEMS_FILE) model_dir = $(build_dir)/$(long_name) @@ -82,5 +83,5 @@ run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regress run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests))) -clean: clean-scala +clean: rm -rf generated-src ./simulator-* diff --git a/vsim/Makefile b/vsim/Makefile index 9baef0cf..1e21e93f 100644 --- a/vsim/Makefile +++ b/vsim/Makefile @@ -28,6 +28,7 @@ rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc sim_vsrcs = \ $(VERILOG_FILE) \ $(HARNESS_FILE) \ + $(HARNESS_SMEMS_FILE) \ $(SMEMS_FILE) VCS = vcs -full64 @@ -62,13 +63,13 @@ $(simv_debug) : $(sim_vsrcs) $(sim_dotf) +define+DEBUG -debug_pp $(output_dir)/%.out: $(output_dir)/% $(simv) - $(simv) +verbose +max-cycles=1000000 $< 3>&1 1>&2 2>&3 | spike-dasm > $@ + $(simv) +permissive -q +ntb_random_seed_automatic +verbose +max-cycles=1000000 +permissive-off $< 3>&1 1>&2 2>&3 | spike-dasm > $@ $(output_dir)/%.run: $(output_dir)/% $(simv) - $(simv) +max-cycles=1000000 $< && touch $@ + $(simv) +permissive -q +ntb_random_seed_automatic +max-cycles=1000000 +permissive-off $< && touch $@ $(output_dir)/%.vpd: $(output_dir)/% $(simv_debug) - $(simv_debug) +vcdplusfile=$@ +max-cycles=1000000 $< + $(simv_debug) +permissive -q +ntb_random_seed_automatic +vcdplusfile=$@ +max-cycles=1000000 +permissive-off $< run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests)))