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This file seems to have missed a scalafmt pass

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chick
2021-08-17 16:14:32 -07:00
parent 143af1aa04
commit db54d55074
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/barstools/macros/Utils.scala
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@@ -55,8 +55,8 @@ class Macro(srcMacro: SRAMMacro) {
val firrtlPorts: Seq[FirrtlMacroPort] = srcMacro.ports.map { new FirrtlMacroPort(_) }
val writers: Seq[FirrtlMacroPort] = firrtlPorts.filter(p => p.isWriter)
val readers: Seq[FirrtlMacroPort] = firrtlPorts.filter(p => p.isReader)
val writers: Seq[FirrtlMacroPort] = firrtlPorts.filter(p => p.isWriter)
val readers: Seq[FirrtlMacroPort] = firrtlPorts.filter(p => p.isReader)
val readwriters: Seq[FirrtlMacroPort] = firrtlPorts.filter(p => p.isReadWriter)
val sortedPorts: Seq[FirrtlMacroPort] = writers ++ readers ++ readwriters