From db54d55074c72470b4916867498a786988ba28b2 Mon Sep 17 00:00:00 2001 From: chick Date: Tue, 17 Aug 2021 16:14:32 -0700 Subject: [PATCH] This file seems to have missed a scalafmt pass --- src/main/scala/barstools/macros/Utils.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/barstools/macros/Utils.scala b/src/main/scala/barstools/macros/Utils.scala index 1b4fa8fe..2bcd116f 100644 --- a/src/main/scala/barstools/macros/Utils.scala +++ b/src/main/scala/barstools/macros/Utils.scala @@ -55,8 +55,8 @@ class Macro(srcMacro: SRAMMacro) { val firrtlPorts: Seq[FirrtlMacroPort] = srcMacro.ports.map { new FirrtlMacroPort(_) } - val writers: Seq[FirrtlMacroPort] = firrtlPorts.filter(p => p.isWriter) - val readers: Seq[FirrtlMacroPort] = firrtlPorts.filter(p => p.isReader) + val writers: Seq[FirrtlMacroPort] = firrtlPorts.filter(p => p.isWriter) + val readers: Seq[FirrtlMacroPort] = firrtlPorts.filter(p => p.isReader) val readwriters: Seq[FirrtlMacroPort] = firrtlPorts.filter(p => p.isReadWriter) val sortedPorts: Seq[FirrtlMacroPort] = writers ++ readers ++ readwriters