diff --git a/src/main/scala/barstools/macros/Utils.scala b/src/main/scala/barstools/macros/Utils.scala
index 1b4fa8fe..2bcd116f 100644
--- a/src/main/scala/barstools/macros/Utils.scala
+++ b/src/main/scala/barstools/macros/Utils.scala
@@ -55,8 +55,8 @@ class Macro(srcMacro: SRAMMacro) {
 
   val firrtlPorts: Seq[FirrtlMacroPort] = srcMacro.ports.map { new FirrtlMacroPort(_) }
 
-  val writers: Seq[FirrtlMacroPort] = firrtlPorts.filter(p => p.isWriter)
-  val readers: Seq[FirrtlMacroPort] = firrtlPorts.filter(p => p.isReader)
+  val writers:     Seq[FirrtlMacroPort] = firrtlPorts.filter(p => p.isWriter)
+  val readers:     Seq[FirrtlMacroPort] = firrtlPorts.filter(p => p.isReader)
   val readwriters: Seq[FirrtlMacroPort] = firrtlPorts.filter(p => p.isReadWriter)
 
   val sortedPorts: Seq[FirrtlMacroPort] = writers ++ readers ++ readwriters