wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Add comment

Browse Source
This commit is contained in:
Edward Wang
2017-07-27 20:35:05 -07:00
committed by edwardcwang
parent b546f49a85
commit d5b30c420b
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
macros/src/main/scala/SynFlops.scala
View File

@@ -31,7 +31,7 @@ class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pa
dataType, dataType,
lib.src.depth, lib.src.depth,
1, // writeLatency 1, // writeLatency
1, // readLatency 1, // readLatency. This is possible because of VerilogMemDelays
lib.readers.indices map (i => s"R_$i"), lib.readers.indices map (i => s"R_$i"),
lib.writers.indices map (i => s"W_$i"), lib.writers.indices map (i => s"W_$i"),
lib.readwriters.indices map (i => s"RW_$i") lib.readwriters.indices map (i => s"RW_$i")