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2017-07-27 20:35:05 -07:00
parent b546f49a85
commit d5b30c420b
1 changed files with 1 additions and 1 deletions
--- a/macros/src/main/scala/SynFlops.scala
+++ b/macros/src/main/scala/SynFlops.scala
@@ -31,7 +31,7 @@ class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pa
      dataType,
      lib.src.depth,
      1, // writeLatency
-      1, // readLatency
+      1, // readLatency. This is possible because of VerilogMemDelays
      lib.readers.indices map (i => s"R_$i"),
      lib.writers.indices map (i => s"W_$i"),
      lib.readwriters.indices map (i => s"RW_$i")