From d5b30c420bd5cc73a06cb61b896bae01062a29ca Mon Sep 17 00:00:00 2001
From: Edward Wang <edward.c.wang@compdigitec.com>
Date: Thu, 27 Jul 2017 20:35:05 -0700
Subject: [PATCH] Add comment

---
 macros/src/main/scala/SynFlops.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/macros/src/main/scala/SynFlops.scala b/macros/src/main/scala/SynFlops.scala
index d33ca43c..48ee368c 100644
--- a/macros/src/main/scala/SynFlops.scala
+++ b/macros/src/main/scala/SynFlops.scala
@@ -31,7 +31,7 @@ class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pa
       dataType,
       lib.src.depth,
       1, // writeLatency
-      1, // readLatency
+      1, // readLatency. This is possible because of VerilogMemDelays
       lib.readers.indices map (i => s"R_$i"),
       lib.writers.indices map (i => s"W_$i"),
       lib.readwriters.indices map (i => s"RW_$i")