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SRAM depth to bigint

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max synflop depth support
Fix annotation mangling on the harness side
This commit is contained in:
Colin Schmidt
2019-05-02 14:36:57 -07:00
committed by Colin Schmidt
parent e548210ef4
commit c23b2b6f84
19 changed files with 383 additions and 276 deletions
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4
macros/src/main/scala/CostMetric.scala
View File

@@ -126,9 +126,9 @@ object DefaultMetric extends CostMetric with CostMetricCompanion {
}
val depthCost = math.ceil(mem.src.depth.toDouble / lib.src.depth.toDouble)
val widthCost = math.ceil(memWidth.toDouble / lib.src.width.toDouble)
val bitsCost = (lib.src.depth * lib.src.width)
val bitsCost = (lib.src.depth * lib.src.width).toDouble
// Fraction of wasted bits plus const per mem
val requestedBits = mem.src.depth * mem.src.width
val requestedBits = (mem.src.depth * mem.src.width).toDouble
val bitsWasted = depthCost*widthCost*bitsCost - requestedBits
val wastedConst = 0.05 // 0 means waste as few bits with no regard for instance count
val costPerInst = wastedConst*depthCost*widthCost

2
macros/src/main/scala/MacroCompiler.scala
View File

@@ -312,7 +312,7 @@ class MacroCompilerPass(mems: Option[Seq[Macro]],
}
}
}
for ((off, i) <- (0 until mem.src.depth by lib.src.depth).zipWithIndex) {
for ((off, i) <- (BigInt(0).until(mem.src.depth, lib.src.depth)).zipWithIndex) {
for (j <- bitPairs.indices) {
val name = s"mem_${i}_${j}"
// Create the instance.

4
macros/src/main/scala/MemConf.scala
View File

@@ -30,7 +30,7 @@ object MemPort {
// TODO standardize this in FIRRTL
case class MemConf(
name: String,
depth: Int,
depth: BigInt,
width: Int,
ports: Seq[MemPort],
maskGranularity: Option[Int]
@@ -51,7 +51,7 @@ object MemConf {
Seq[MemConf]()
} else {
s.split("\n").toSeq.map(_ match {
case MemConf.regex(name, depth, width, ports, maskGran) => MemConf(name, depth.toInt, width.toInt, MemPort.fromString(ports), Option(maskGran).map(_.toInt))
case MemConf.regex(name, depth, width, ports, maskGran) => MemConf(name, BigInt(depth), width.toInt, MemPort.fromString(ports), Option(maskGran).map(_.toInt))
case _ => throw new Exception(s"Error parsing MemConf string : ${s}")
})
}

94
macros/src/main/scala/SynFlops.scala
View File

@@ -9,8 +9,9 @@ import firrtl.passes.MemPortUtils.{memPortField, memType}
import Utils._
class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pass {
val extraMods = scala.collection.mutable.ArrayBuffer.empty[Module]
lazy val libMods = (libs map { lib => lib.src.name -> {
val dataType = (lib.src.ports foldLeft (None: Option[BigInt]))((res, port) =>
val (dataType, dataWidth) = (lib.src.ports foldLeft (None: Option[BigInt]))((res, port) =>
(res, port.maskPort) match {
case (_, None) =>
res
@@ -21,23 +22,35 @@ class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pa
res
}
) match {
case None => UIntType(IntWidth(lib.src.width))
case Some(gran) => VectorType(UIntType(IntWidth(gran)), (lib.src.width / gran).toInt)
case None => (UIntType(IntWidth(lib.src.width)), lib.src.width)
case Some(gran) => (UIntType(IntWidth(gran)), gran.intValue)
}
val maxDepth = min(lib.src.depth, 1<<26)
val numMems = lib.src.depth / maxDepth
// Change macro to be mapped onto to look like the below mem
// by changing its depth, and width
val lib_macro = new Macro(lib.src.copy(name="split_"+lib.src.name,
depth = maxDepth, width = dataWidth, ports = lib.src.ports.map(p =>
p.copy(width = p.width.map(_ => dataWidth), depth = p.depth.map(_ => maxDepth),
maskGran = p.maskGran.map(_ => dataWidth)))))
val mod_macro = (new MacroCompilerPass(None,None,None,None)).compile(lib, lib_macro)
val (real_mod, real_macro) = mod_macro.get
val mem = DefMemory(
NoInfo,
"ram",
dataType,
lib.src.depth,
maxDepth,
1, // writeLatency
1, // readLatency. This is possible because of VerilogMemDelays
lib.readers.indices map (i => s"R_$i"),
lib.writers.indices map (i => s"W_$i"),
lib.readwriters.indices map (i => s"RW_$i")
real_macro.readers.indices map (i => s"R_$i"),
real_macro.writers.indices map (i => s"W_$i"),
real_macro.readwriters.indices map (i => s"RW_$i")
)
val readConnects = lib.readers.zipWithIndex flatMap { case (r, i) =>
val readConnects = real_macro.readers.zipWithIndex flatMap { case (r, i) =>
val clock = portToExpression(r.src.clock.get)
val address = portToExpression(r.src.address)
val enable = (r.src chipEnable, r.src readEnable) match {
@@ -49,11 +62,7 @@ class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pa
case (None, None) => one
}
val data = memPortField(mem, s"R_$i", "data")
val read = (dataType: @unchecked) match {
case VectorType(tpe, size) => cat(((0 until size) map (k =>
WSubIndex(data, k, tpe, UNKNOWNGENDER))).reverse)
case _: UIntType => data
}
val read = data
Seq(
Connect(NoInfo, memPortField(mem, s"R_$i", "clk"), clock),
Connect(NoInfo, memPortField(mem, s"R_$i", "addr"), address),
@@ -62,7 +71,7 @@ class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pa
)
}
val writeConnects = lib.writers.zipWithIndex flatMap { case (w, i) =>
val writeConnects = real_macro.writers.zipWithIndex flatMap { case (w, i) =>
val clock = portToExpression(w.src.clock.get)
val address = portToExpression(w.src.address)
val enable = (w.src.chipEnable, w.src.writeEnable) match {
@@ -73,34 +82,32 @@ class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pa
case (None, Some(we)) => portToExpression(we)
case (None, None) => zero // is it possible?
}
val mask = memPortField(mem, s"W_$i", "mask")
val mask = w.src.maskPort match {
case Some(m) => portToExpression(m)
case None => one
}
val data = memPortField(mem, s"W_$i", "data")
val write = portToExpression(w.src.input.get)
Seq(
Connect(NoInfo, memPortField(mem, s"W_$i", "clk"), clock),
Connect(NoInfo, memPortField(mem, s"W_$i", "addr"), address),
Connect(NoInfo, memPortField(mem, s"W_$i", "en"), enable)
) ++ (dataType match {
case VectorType(tpe, size) =>
val width = bitWidth(tpe).toInt
((0 until size) map (k =>
Connect(NoInfo, WSubIndex(data, k, tpe, UNKNOWNGENDER),
bits(write, (k + 1) * width - 1, k * width)))) ++
((0 until size) map (k =>
Connect(NoInfo, WSubIndex(mask, k, BoolType, UNKNOWNGENDER),
bits(WRef(w.src.maskPort.get.name), k))))
case _: UIntType =>
Seq(Connect(NoInfo, data, write), Connect(NoInfo, mask, one))
})
Connect(NoInfo, memPortField(mem, s"W_$i", "en"), enable),
Connect(NoInfo, memPortField(mem, s"W_$i", "mask"), mask),
Connect(NoInfo, data, write)
)
}
val readwriteConnects = lib.readwriters.zipWithIndex flatMap { case (rw, i) =>
val readwriteConnects = real_macro.readwriters.zipWithIndex flatMap { case (rw, i) =>
val clock = portToExpression(rw.src.clock.get)
val address = portToExpression(rw.src.address)
val wmode = rw.src.writeEnable match {
case Some(we) => portToExpression(we)
case None => zero // is it possible?
}
val wmask = rw.src.maskPort match {
case Some(wm) => portToExpression(wm)
case None => one
}
val enable = (rw.src.chipEnable, rw.src.readEnable) match {
case (Some(en), Some(re)) =>
and(portToExpression(en), or(portToExpression(re), wmode))
@@ -108,40 +115,27 @@ class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pa
case (None, Some(re)) => or(portToExpression(re), wmode)
case (None, None) => one
}
val wmask = memPortField(mem, s"RW_$i", "wmask")
val wdata = memPortField(mem, s"RW_$i", "wdata")
val rdata = memPortField(mem, s"RW_$i", "rdata")
val write = portToExpression(rw.src.input.get)
val read = (dataType: @unchecked) match {
case VectorType(tpe, size) => cat(((0 until size) map (k =>
WSubIndex(rdata, k, tpe, UNKNOWNGENDER))).reverse)
case _: UIntType => rdata
}
val read = rdata
Seq(
Connect(NoInfo, memPortField(mem, s"RW_$i", "clk"), clock),
Connect(NoInfo, memPortField(mem, s"RW_$i", "addr"), address),
Connect(NoInfo, memPortField(mem, s"RW_$i", "en"), enable),
Connect(NoInfo, memPortField(mem, s"RW_$i", "wmode"), wmode),
Connect(NoInfo, WRef(rw.src.output.get.name), read)
) ++ (dataType match {
case VectorType(tpe, size) =>
val width = bitWidth(tpe).toInt
((0 until size) map (k =>
Connect(NoInfo, WSubIndex(wdata, k, tpe, UNKNOWNGENDER),
bits(write, (k + 1) * width - 1, k * width)))) ++
((0 until size) map (k =>
Connect(NoInfo, WSubIndex(wmask, k, BoolType, UNKNOWNGENDER),
bits(WRef(rw.src.maskPort.get.name), k))))
case _: UIntType =>
Seq(Connect(NoInfo, wdata, write), Connect(NoInfo, wmask, one))
})
Connect(NoInfo, memPortField(mem, s"RW_$i", "wmask"), wmask),
Connect(NoInfo, WRef(rw.src.output.get.name), read),
Connect(NoInfo, wdata, write)
)
}
lib.module(Block(mem +: (readConnects ++ writeConnects ++ readwriteConnects)))
extraMods.append(real_macro.module(Block(mem +: (readConnects ++ writeConnects ++ readwriteConnects))))
real_mod
}}).toMap
def run(c: Circuit): Circuit = {
if (!synflops) c
else c.copy(modules = (c.modules map (m => libMods getOrElse (m.name, m))))
else c.copy(modules = (c.modules map (m => libMods.getOrElse(m.name, m))) ++ extraMods)
}
}

4
macros/src/main/scala/Utils.scala
View File

@@ -91,7 +91,7 @@ object Utils {
return numRStr + numWStr + numRWStr
}
// This translates between two represenations of ports
def portSpecToMacroPort(width: Int, depth: Int, maskGran: Option[Int], ports: Seq[MemPort]): Seq[MacroPort] = {
def portSpecToMacroPort(width: Int, depth: BigInt, maskGran: Option[Int], ports: Seq[MemPort]): Seq[MacroPort] = {
var numR = 0
var numW = 0
var numRW = 0
@@ -103,7 +103,7 @@ object Utils {
width=Some(width), depth=Some(depth),
address=PolarizedPort(s"${portName}_addr", ActiveHigh),
clock=Some(PolarizedPort(s"${portName}_clk", PositiveEdge)),
chipEnable=Some(PolarizedPort(s"${portName}_en", ActiveHigh)),
readEnable=Some(PolarizedPort(s"${portName}_en", ActiveHigh)),
output=Some(PolarizedPort(s"${portName}_data", ActiveHigh))
) }
case WritePort => {

70
macros/src/test/resources/lib-BOOMTest.json
View File

@@ -22,7 +22,7 @@
],
"name": "my_sram_1rw_1024x8",
"type": "sram",
"depth": 1024
"depth": "1024"
},
{
"family": "1rw",
@@ -47,7 +47,7 @@
],
"name": "my_sram_1rw_128x46",
"type": "sram",
"depth": 128
"depth": "128"
},
{
"family": "1rw",
@@ -72,7 +72,7 @@
],
"name": "my_sram_1rw_128x48",
"type": "sram",
"depth": 128
"depth": "128"
},
{
"family": "1rw",
@@ -97,7 +97,7 @@
],
"name": "my_sram_1rw_128x8",
"type": "sram",
"depth": 128
"depth": "128"
},
{
"family": "1rw",
@@ -122,7 +122,7 @@
],
"name": "my_sram_1rw_256x128",
"type": "sram",
"depth": 256
"depth": "256"
},
{
"family": "1rw",
@@ -147,7 +147,7 @@
],
"name": "my_sram_1rw_256x32",
"type": "sram",
"depth": 256
"depth": "256"
},
{
"family": "1rw",
@@ -172,7 +172,7 @@
],
"name": "my_sram_1rw_256x46",
"type": "sram",
"depth": 256
"depth": "256"
},
{
"family": "1rw",
@@ -197,7 +197,7 @@
],
"name": "my_sram_1rw_256x48",
"type": "sram",
"depth": 256
"depth": "256"
},
{
"family": "1rw",
@@ -222,7 +222,7 @@
],
"name": "my_sram_1rw_256x8",
"type": "sram",
"depth": 256
"depth": "256"
},
{
"family": "1rw",
@@ -247,7 +247,7 @@
],
"name": "my_sram_1rw_32x50",
"type": "sram",
"depth": 32
"depth": "32"
},
{
"family": "1rw",
@@ -272,7 +272,7 @@
],
"name": "my_sram_1rw_512x128",
"type": "sram",
"depth": 512
"depth": "512"
},
{
"family": "1rw",
@@ -297,7 +297,7 @@
],
"name": "my_sram_1rw_512x32",
"type": "sram",
"depth": 512
"depth": "512"
},
{
"family": "1rw",
@@ -322,7 +322,7 @@
],
"name": "my_sram_1rw_512x8",
"type": "sram",
"depth": 512
"depth": "512"
},
{
"family": "1rw",
@@ -347,7 +347,7 @@
],
"name": "my_sram_1rw_64x128",
"type": "sram",
"depth": 64
"depth": "64"
},
{
"family": "1rw",
@@ -372,7 +372,7 @@
],
"name": "my_sram_1rw_64x32",
"type": "sram",
"depth": 64
"depth": "64"
},
{
"family": "1rw",
@@ -397,7 +397,7 @@
],
"name": "my_sram_1rw_64x34",
"type": "sram",
"depth": 64
"depth": "64"
},
{
"family": "1rw",
@@ -422,7 +422,7 @@
],
"name": "my_sram_1rw_64x8",
"type": "sram",
"depth": 64
"depth": "64"
},
{
"family": "2rw",
@@ -463,7 +463,7 @@
],
"name": "my_sram_2rw_128x16",
"type": "sram",
"depth": 128
"depth": "128"
},
{
"family": "2rw",
@@ -504,7 +504,7 @@
],
"name": "my_sram_2rw_128x32",
"type": "sram",
"depth": 128
"depth": "128"
},
{
"family": "2rw",
@@ -545,7 +545,7 @@
],
"name": "my_sram_2rw_128x4",
"type": "sram",
"depth": 128
"depth": "128"
},
{
"family": "2rw",
@@ -586,7 +586,7 @@
],
"name": "my_sram_2rw_128x8",
"type": "sram",
"depth": 128
"depth": "128"
},
{
"family": "2rw",
@@ -627,7 +627,7 @@
],
"name": "my_sram_2rw_16x16",
"type": "sram",
"depth": 16
"depth": "16"
},
{
"family": "2rw",
@@ -668,7 +668,7 @@
],
"name": "my_sram_2rw_16x32",
"type": "sram",
"depth": 16
"depth": "16"
},
{
"family": "2rw",
@@ -709,7 +709,7 @@
],
"name": "my_sram_2rw_16x4",
"type": "sram",
"depth": 16
"depth": "16"
},
{
"family": "2rw",
@@ -750,7 +750,7 @@
],
"name": "my_sram_2rw_16x8",
"type": "sram",
"depth": 16
"depth": "16"
},
{
"family": "2rw",
@@ -791,7 +791,7 @@
],
"name": "my_sram_2rw_32x16",
"type": "sram",
"depth": 32
"depth": "32"
},
{
"family": "2rw",
@@ -832,7 +832,7 @@
],
"name": "my_sram_2rw_32x22",
"type": "sram",
"depth": 32
"depth": "32"
},
{
"family": "2rw",
@@ -873,7 +873,7 @@
],
"name": "my_sram_2rw_32x32",
"type": "sram",
"depth": 32
"depth": "32"
},
{
"family": "2rw",
@@ -914,7 +914,7 @@
],
"name": "my_sram_2rw_32x39",
"type": "sram",
"depth": 32
"depth": "32"
},
{
"family": "2rw",
@@ -955,7 +955,7 @@
],
"name": "my_sram_2rw_32x4",
"type": "sram",
"depth": 32
"depth": "32"
},
{
"family": "2rw",
@@ -996,7 +996,7 @@
],
"name": "my_sram_2rw_32x8",
"type": "sram",
"depth": 32
"depth": "32"
},
{
"family": "2rw",
@@ -1037,7 +1037,7 @@
],
"name": "my_sram_2rw_64x16",
"type": "sram",
"depth": 64
"depth": "64"
},
{
"family": "2rw",
@@ -1078,7 +1078,7 @@
],
"name": "my_sram_2rw_64x32",
"type": "sram",
"depth": 64
"depth": "64"
},
{
"family": "2rw",
@@ -1119,7 +1119,7 @@
],
"name": "my_sram_2rw_64x4",
"type": "sram",
"depth": 64
"depth": "64"
},
{
"family": "2rw",
@@ -1160,6 +1160,6 @@
],
"name": "my_sram_2rw_64x8",
"type": "sram",
"depth": 64
"depth": "64"
}
]

14
macros/src/test/scala/CostFunction.scala
View File

@@ -31,34 +31,34 @@ class SelectCostMetric extends MacroCompilerSpec with HasSRAMGenerator {
val libSRAMs = Seq(
SRAMMacro(
name="SRAM_WIDTH_128",
depth=1024,
depth=BigInt(1024),
width=128,
family="1rw",
ports=Seq(
generateReadWritePort("", 128, 1024)
generateReadWritePort("", 128, BigInt(1024))
)
),
SRAMMacro(
name="SRAM_WIDTH_64",
depth=1024,
depth=BigInt(1024),
width=64,
family="1rw",
ports=Seq(
generateReadWritePort("", 64, 1024)
generateReadWritePort("", 64, BigInt(1024))
)
),
SRAMMacro(
name="SRAM_WIDTH_32",
depth=1024,
depth=BigInt(1024),
width=32,
family="1rw",
ports=Seq(
generateReadWritePort("", 32, 1024)
generateReadWritePort("", 32, BigInt(1024))
)
)
)
val memSRAMs = Seq(generateSRAM("target_memory", "", 128, 1024))
val memSRAMs = Seq(generateSRAM("target_memory", "", 128, BigInt(1024)))
writeToLib(lib, libSRAMs)
writeToMem(mem, memSRAMs)

8
macros/src/test/scala/Functional.scala
View File

@@ -7,8 +7,8 @@ import firrtl_interpreter.InterpretiveTester
// Synchronous write and read back.
class SynchronousReadAndWrite extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 12
override lazy val memDepth = 2048
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(2048)
override lazy val libDepth = BigInt(1024)
compile(mem, lib, v, true)
val result = execute(mem, lib, true)
@@ -67,8 +67,8 @@ class SynchronousReadAndWrite extends MacroCompilerSpec with HasSRAMGenerator wi
// between two submemories.
class DontReadCombinationally extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 8
override lazy val memDepth = 2048
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(2048)
override lazy val libDepth = BigInt(1024)
compile(mem, lib, v, true)
val result = execute(mem, lib, true)

18
macros/src/test/scala/MacroCompilerSpec.scala
View File

@@ -122,6 +122,7 @@ trait HasSRAMGenerator {
import mdf.macrolib._
import scala.language.implicitConversions
implicit def Int2SomeInt(i: Int): Option[Int] = Some(i)
implicit def BigInt2SomeBigInt(i: BigInt): Option[BigInt] = Some(i)
// Generate a standard (read/write/combo) port for testing.
@@ -129,7 +130,7 @@ trait HasSRAMGenerator {
def generateTestPort(
prefix: String,
width: Option[Int],
depth: Option[Int],
depth: Option[BigInt],
maskGran: Option[Int] = None,
read: Boolean,
readEnable: Boolean = false,
@@ -159,17 +160,17 @@ trait HasSRAMGenerator {
}
// Generate a read port for testing.
def generateReadPort(prefix: String, width: Option[Int], depth: Option[Int], readEnable: Boolean = false): MacroPort = {
def generateReadPort(prefix: String, width: Option[Int], depth: Option[BigInt], readEnable: Boolean = false): MacroPort = {
generateTestPort(prefix, width, depth, write = false, read = true, readEnable = readEnable)
}
// Generate a write port for testing.
def generateWritePort(prefix: String, width: Option[Int], depth: Option[Int], maskGran: Option[Int] = None, writeEnable: Boolean = true): MacroPort = {
def generateWritePort(prefix: String, width: Option[Int], depth: Option[BigInt], maskGran: Option[Int] = None, writeEnable: Boolean = true): MacroPort = {
generateTestPort(prefix, width, depth, maskGran = maskGran, write = true, read = false, writeEnable = writeEnable)
}
// Generate a simple read-write port for testing.
def generateReadWritePort(prefix: String, width: Option[Int], depth: Option[Int], maskGran: Option[Int] = None): MacroPort = {
def generateReadWritePort(prefix: String, width: Option[Int], depth: Option[BigInt], maskGran: Option[Int] = None): MacroPort = {
generateTestPort(
prefix, width, depth, maskGran = maskGran,
write = true, writeEnable = true,
@@ -178,7 +179,7 @@ trait HasSRAMGenerator {
}
// Generate a "simple" SRAM (active high/positive edge, 1 read-write port).
def generateSRAM(name: String, prefix: String, width: Int, depth: Int, maskGran: Option[Int] = None, extraPorts: Seq[MacroExtraPort] = List()): SRAMMacro = {
def generateSRAM(name: String, prefix: String, width: Int, depth: BigInt, maskGran: Option[Int] = None, extraPorts: Seq[MacroExtraPort] = List()): SRAMMacro = {
SRAMMacro(
name = name,
width = width,
@@ -215,8 +216,8 @@ trait HasSimpleTestGenerator {
def useCompiler: Boolean = false
def memWidth: Int
def libWidth: Int
def memDepth: Int
def libDepth: Int
def memDepth: BigInt
def libDepth: BigInt
def memMaskGran: Option[Int] = None
def libMaskGran: Option[Int] = None
def extraPorts: Seq[mdf.macrolib.MacroExtraPort] = List()
@@ -276,7 +277,7 @@ trait HasSimpleTestGenerator {
// Number of lib instances needed to hold the mem, in both directions.
// Round up (e.g. 1.5 instances = effectively 2 instances)
val depthInstances = math.ceil(memDepth.toFloat / libDepth).toInt
val depthInstances = math.ceil(memDepth.toFloat / libDepth.toFloat).toInt
val widthInstances = math.ceil(memWidth.toFloat / usableLibWidth).toInt
// Number of width bits in the last width-direction memory.
@@ -440,6 +441,7 @@ trait HasNoLibTestGenerator extends HasSimpleTestGenerator {
// Therefore, make "lib" width/depth equal to the mem.
override lazy val libDepth = memDepth
override lazy val libWidth = memWidth
override lazy val lib_name = mem_name
// Do the same for port names.
override lazy val libPortPrefix = memPortPrefix

20
macros/src/test/scala/Masks.scala
View File

@@ -6,8 +6,8 @@ import mdf.macrolib._
trait MasksTestSettings {
this: MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator =>
override lazy val memDepth = 2048
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(2048)
override lazy val libDepth = BigInt(1024)
}
// Try all four different kinds of mask config:
@@ -22,7 +22,7 @@ trait MasksTestSettings {
*/
class Masks_FourTypes_NonMaskedMem_NonMaskedLib extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 32
override lazy val memMaskGran = None
override lazy val libWidth = 8
@@ -32,7 +32,7 @@ class Masks_FourTypes_NonMaskedMem_NonMaskedLib extends MacroCompilerSpec with H
}
class Masks_FourTypes_NonMaskedMem_MaskedLib extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 32
override lazy val memMaskGran = None
override lazy val libWidth = 8
@@ -42,7 +42,7 @@ class Masks_FourTypes_NonMaskedMem_MaskedLib extends MacroCompilerSpec with HasS
}
class Masks_FourTypes_MaskedMem_NonMaskedLib extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 32
override lazy val memMaskGran = Some(8)
override lazy val libWidth = 8
@@ -52,7 +52,7 @@ class Masks_FourTypes_MaskedMem_NonMaskedLib extends MacroCompilerSpec with HasS
}
class Masks_FourTypes_MaskedMem_NonMaskedLib_SmallerMaskGran extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 32
override lazy val memMaskGran = Some(4)
override lazy val libWidth = 8
@@ -62,7 +62,7 @@ class Masks_FourTypes_MaskedMem_NonMaskedLib_SmallerMaskGran extends MacroCompil
}
class Masks_FourTypes_MaskedMem_MaskedLib extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 32
override lazy val memMaskGran = Some(8)
override lazy val libWidth = 16
@@ -72,7 +72,7 @@ class Masks_FourTypes_MaskedMem_MaskedLib extends MacroCompilerSpec with HasSRAM
}
class Masks_FourTypes_MaskedMem_MaskedLib_SameMaskGran extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 32
override lazy val memMaskGran = Some(8)
override lazy val libWidth = 16
@@ -82,7 +82,7 @@ class Masks_FourTypes_MaskedMem_MaskedLib_SameMaskGran extends MacroCompilerSpec
}
class Masks_FourTypes_MaskedMem_MaskedLib_SmallerMaskGran extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 64
override lazy val memMaskGran = Some(4)
override lazy val libWidth = 32
@@ -94,7 +94,7 @@ class Masks_FourTypes_MaskedMem_MaskedLib_SmallerMaskGran extends MacroCompilerS
// Bit-mask memories to non-masked libs whose width is larger than 1.
class Masks_BitMaskedMem_NonMaskedLib extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 16
override lazy val memMaskGran = Some(1)
override lazy val libWidth = 8

18
macros/src/test/scala/MultiPort.scala
View File

@@ -6,7 +6,7 @@ package barstools.macros
class SplitWidth_2rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
import mdf.macrolib._
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 64
override lazy val memMaskGran = Some(16)
override lazy val libWidth = 16
@@ -18,11 +18,11 @@ class SplitWidth_2rw extends MacroCompilerSpec with HasSRAMGenerator with HasSim
depth=memDepth,
family="2rw",
ports=Seq(generateTestPort(
"portA", memWidth, memDepth, maskGran=memMaskGran,
"portA", memWidth, Some(memDepth), maskGran=memMaskGran,
write=true, writeEnable=true,
read=true, readEnable=true
), generateTestPort(
"portB", memWidth, memDepth, maskGran=memMaskGran,
"portB", memWidth, Some(memDepth), maskGran=memMaskGran,
write=true, writeEnable=true,
read=true, readEnable=true
))
@@ -121,7 +121,7 @@ class SplitWidth_2rw extends MacroCompilerSpec with HasSRAMGenerator with HasSim
class SplitWidth_1r_1w extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
import mdf.macrolib._
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 64
override lazy val memMaskGran = Some(16)
override lazy val libWidth = 16
@@ -133,11 +133,11 @@ class SplitWidth_1r_1w extends MacroCompilerSpec with HasSRAMGenerator with HasS
depth=memDepth,
family="1r1w",
ports=Seq(generateTestPort(
"portA", memWidth, memDepth, maskGran=memMaskGran,
"portA", memWidth, Some(memDepth), maskGran=memMaskGran,
write=false, writeEnable=false,
read=true, readEnable=true
), generateTestPort(
"portB", memWidth, memDepth, maskGran=memMaskGran,
"portB", memWidth, Some(memDepth), maskGran=memMaskGran,
write=true, writeEnable=true,
read=false, readEnable=false
))
@@ -224,7 +224,7 @@ class SplitWidth_1r_1w extends MacroCompilerSpec with HasSRAMGenerator with HasS
class SplitWidth_2rw_differentMasks extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
import mdf.macrolib._
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 64
override lazy val memMaskGran = Some(16)
override lazy val libWidth = 16
@@ -239,11 +239,11 @@ class SplitWidth_2rw_differentMasks extends MacroCompilerSpec with HasSRAMGenera
depth=memDepth,
family="2rw",
ports=Seq(generateTestPort(
"portA", memWidth, memDepth, maskGran=memMaskGran,
"portA", memWidth, Some(memDepth), maskGran=memMaskGran,
write=true, writeEnable=true,
read=true, readEnable=true
), generateTestPort(
"portB", memWidth, memDepth, maskGran=Some(memMaskGranB),
"portB", memWidth, Some(memDepth), maskGran=Some(memMaskGranB),
write=true, writeEnable=true,
read=true, readEnable=true
))

2
macros/src/test/scala/SRAMCompiler.scala
View File

@@ -5,7 +5,7 @@ import mdf.macrolib._
class SRAMCompiler extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
val compiler = generateSRAMCompiler("awesome", "A")
val verilog = s"v-SRAMCompiler.v"
override lazy val depth = 16
override lazy val depth = BigInt(16)
override lazy val memWidth = 8
override lazy val libWidth = 8
override lazy val mem_name = "mymem"

84
macros/src/test/scala/SimpleSplitDepth.scala
View File

@@ -67,48 +67,48 @@ s"""
// Try different widths
class SplitDepth4096x32_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 32
override lazy val memDepth = 4096
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(4096)
override lazy val libDepth = BigInt(1024)
compileExecuteAndTest(mem, lib, v, output)
}
class SplitDepth4096x16_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 16
override lazy val memDepth = 4096
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(4096)
override lazy val libDepth = BigInt(1024)
compileExecuteAndTest(mem, lib, v, output)
}
class SplitDepth32768x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 8
override lazy val memDepth = 32768
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(32768)
override lazy val libDepth = BigInt(1024)
compileExecuteAndTest(mem, lib, v, output)
}
class SplitDepth4096x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 8
override lazy val memDepth = 4096
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(4096)
override lazy val libDepth = BigInt(1024)
compileExecuteAndTest(mem, lib, v, output)
}
class SplitDepth2048x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 8
override lazy val memDepth = 2048
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(2048)
override lazy val libDepth = BigInt(1024)
compileExecuteAndTest(mem, lib, v, output)
}
class SplitDepth1024x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 8
override lazy val memDepth = 1024
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(1024)
override lazy val libDepth = BigInt(1024)
compileExecuteAndTest(mem, lib, v, output)
}
@@ -116,16 +116,16 @@ class SplitDepth1024x8_rw extends MacroCompilerSpec with HasSRAMGenerator with H
// Non power of two
class SplitDepth2000x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 8
override lazy val memDepth = 2000
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(2000)
override lazy val libDepth = BigInt(1024)
compileExecuteAndTest(mem, lib, v, output)
}
class SplitDepth2049x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 8
override lazy val memDepth = 2049
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(2049)
override lazy val libDepth = BigInt(1024)
compileExecuteAndTest(mem, lib, v, output)
}
@@ -135,8 +135,8 @@ class SplitDepth2049x8_rw extends MacroCompilerSpec with HasSRAMGenerator with H
// Test for mem mask == lib mask (i.e. mask is a write enable bit)
class SplitDepth2048x32_mrw_lib32 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 32
override lazy val memDepth = 2048
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(2048)
override lazy val libDepth = BigInt(1024)
override lazy val memMaskGran = Some(32)
override lazy val libMaskGran = Some(32)
@@ -145,8 +145,8 @@ class SplitDepth2048x32_mrw_lib32 extends MacroCompilerSpec with HasSRAMGenerato
class SplitDepth2048x8_mrw_lib8 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 8
override lazy val memDepth = 2048
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(2048)
override lazy val libDepth = BigInt(1024)
override lazy val memMaskGran = Some(8)
override lazy val libMaskGran = Some(8)
@@ -156,8 +156,8 @@ class SplitDepth2048x8_mrw_lib8 extends MacroCompilerSpec with HasSRAMGenerator
// Non-bit level mask
class SplitDepth2048x64_mrw_mem32_lib8 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 64
override lazy val memDepth = 2048
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(2048)
override lazy val libDepth = BigInt(1024)
override lazy val memMaskGran = Some(32)
override lazy val libMaskGran = Some(8)
@@ -167,8 +167,8 @@ class SplitDepth2048x64_mrw_mem32_lib8 extends MacroCompilerSpec with HasSRAMGen
// Bit level mask
class SplitDepth2048x32_mrw_mem16_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 32
override lazy val memDepth = 2048
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(2048)
override lazy val libDepth = BigInt(1024)
override lazy val memMaskGran = Some(16)
override lazy val libMaskGran = Some(1)
@@ -177,8 +177,8 @@ class SplitDepth2048x32_mrw_mem16_lib1 extends MacroCompilerSpec with HasSRAMGen
class SplitDepth2048x32_mrw_mem8_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 32
override lazy val memDepth = 2048
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(2048)
override lazy val libDepth = BigInt(1024)
override lazy val memMaskGran = Some(8)
override lazy val libMaskGran = Some(1)
@@ -187,8 +187,8 @@ class SplitDepth2048x32_mrw_mem8_lib1 extends MacroCompilerSpec with HasSRAMGene
class SplitDepth2048x32_mrw_mem4_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 32
override lazy val memDepth = 2048
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(2048)
override lazy val libDepth = BigInt(1024)
override lazy val memMaskGran = Some(4)
override lazy val libMaskGran = Some(1)
@@ -197,8 +197,8 @@ class SplitDepth2048x32_mrw_mem4_lib1 extends MacroCompilerSpec with HasSRAMGene
class SplitDepth2048x32_mrw_mem2_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 32
override lazy val memDepth = 2048
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(2048)
override lazy val libDepth = BigInt(1024)
override lazy val memMaskGran = Some(2)
override lazy val libMaskGran = Some(1)
@@ -208,8 +208,8 @@ class SplitDepth2048x32_mrw_mem2_lib1 extends MacroCompilerSpec with HasSRAMGene
// Non-powers of 2 mask sizes
class SplitDepth2048x32_mrw_mem3_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 32
override lazy val memDepth = 2048
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(2048)
override lazy val libDepth = BigInt(1024)
override lazy val memMaskGran = Some(3)
override lazy val libMaskGran = Some(1)
@@ -219,8 +219,8 @@ class SplitDepth2048x32_mrw_mem3_lib1 extends MacroCompilerSpec with HasSRAMGene
class SplitDepth2048x32_mrw_mem7_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 32
override lazy val memDepth = 2048
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(2048)
override lazy val libDepth = BigInt(1024)
override lazy val memMaskGran = Some(7)
override lazy val libMaskGran = Some(1)
@@ -230,8 +230,8 @@ class SplitDepth2048x32_mrw_mem7_lib1 extends MacroCompilerSpec with HasSRAMGene
class SplitDepth2048x32_mrw_mem9_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 32
override lazy val memDepth = 2048
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(2048)
override lazy val libDepth = BigInt(1024)
override lazy val memMaskGran = Some(9)
override lazy val libMaskGran = Some(1)
@@ -244,8 +244,8 @@ class SplitDepth2048x8_extraPort extends MacroCompilerSpec with HasSRAMGenerator
import mdf.macrolib._
override lazy val width = 8
override lazy val memDepth = 2048
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(2048)
override lazy val libDepth = BigInt(1024)
override lazy val extraPorts = List(
MacroExtraPort(name="extra_port", width=8, portType=Constant, value=0xff)
)
@@ -303,8 +303,8 @@ circuit target_memory :
// Split read and (non-masked) write ports (r+w).
class SplitDepth_SplitPortsNonMasked extends MacroCompilerSpec with HasSRAMGenerator {
lazy val width = 8
lazy val memDepth = 2048
lazy val libDepth = 1024
lazy val memDepth = BigInt(2048)
lazy val libDepth = BigInt(1024)
override val memPrefix = testDir
override val libPrefix = testDir
@@ -462,8 +462,8 @@ TODO
// Split read and (masked) write ports (r+mw).
class SplitDepth_SplitPortsMasked extends MacroCompilerSpec with HasSRAMGenerator {
lazy val width = 8
lazy val memDepth = 2048
lazy val libDepth = 1024
lazy val memDepth = BigInt(2048)
lazy val libDepth = BigInt(1024)
lazy val memMaskGran = Some(8)
lazy val libMaskGran = Some(1)

78
macros/src/test/scala/SimpleSplitWidth.scala
View File

@@ -5,7 +5,7 @@ package barstools.macros
trait HasSimpleWidthTestGenerator extends HasSimpleTestGenerator {
this: MacroCompilerSpec with HasSRAMGenerator =>
def depth: Int
def depth: BigInt
override lazy val memDepth = depth
override lazy val libDepth = depth
@@ -69,7 +69,7 @@ s"""
// Try different widths against a base memory width of 8.
class SplitWidth1024x128_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 128
override lazy val libWidth = 8
@@ -77,7 +77,7 @@ class SplitWidth1024x128_rw extends MacroCompilerSpec with HasSRAMGenerator with
}
class SplitWidth1024x64_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 64
override lazy val libWidth = 8
@@ -85,7 +85,7 @@ class SplitWidth1024x64_rw extends MacroCompilerSpec with HasSRAMGenerator with
}
class SplitWidth1024x32_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 32
override lazy val libWidth = 8
@@ -93,7 +93,7 @@ class SplitWidth1024x32_rw extends MacroCompilerSpec with HasSRAMGenerator with
}
class SplitWidth1024x16_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 16
override lazy val libWidth = 8
@@ -101,7 +101,7 @@ class SplitWidth1024x16_rw extends MacroCompilerSpec with HasSRAMGenerator with
}
class SplitWidth1024x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 8
override lazy val libWidth = 8
@@ -110,7 +110,7 @@ class SplitWidth1024x8_rw extends MacroCompilerSpec with HasSRAMGenerator with H
// Try different widths against a base memory width of 16.
class SplitWidth1024x128_lib16_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 128
override lazy val libWidth = 16
@@ -118,7 +118,7 @@ class SplitWidth1024x128_lib16_rw extends MacroCompilerSpec with HasSRAMGenerato
}
class SplitWidth1024x64_lib16_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 64
override lazy val libWidth = 16
@@ -126,7 +126,7 @@ class SplitWidth1024x64_lib16_rw extends MacroCompilerSpec with HasSRAMGenerator
}
class SplitWidth1024x32_lib16_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 32
override lazy val libWidth = 16
@@ -134,7 +134,7 @@ class SplitWidth1024x32_lib16_rw extends MacroCompilerSpec with HasSRAMGenerator
}
class SplitWidth1024x16_lib16_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 16
override lazy val libWidth = 16
@@ -143,7 +143,7 @@ class SplitWidth1024x16_lib16_rw extends MacroCompilerSpec with HasSRAMGenerator
// Try different widths against a base memory width of 8 but depth 512 instead of 1024.
class SplitWidth512x128_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 512
override lazy val depth = BigInt(512)
override lazy val memWidth = 128
override lazy val libWidth = 8
@@ -151,7 +151,7 @@ class SplitWidth512x128_rw extends MacroCompilerSpec with HasSRAMGenerator with
}
class SplitWidth512x64_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 512
override lazy val depth = BigInt(512)
override lazy val memWidth = 64
override lazy val libWidth = 8
@@ -159,7 +159,7 @@ class SplitWidth512x64_rw extends MacroCompilerSpec with HasSRAMGenerator with H
}
class SplitWidth512x32_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 512
override lazy val depth = BigInt(512)
override lazy val memWidth = 32
override lazy val libWidth = 8
@@ -167,7 +167,7 @@ class SplitWidth512x32_rw extends MacroCompilerSpec with HasSRAMGenerator with H
}
class SplitWidth512x16_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 512
override lazy val depth = BigInt(512)
override lazy val memWidth = 16
override lazy val libWidth = 8
@@ -175,7 +175,7 @@ class SplitWidth512x16_rw extends MacroCompilerSpec with HasSRAMGenerator with H
}
class SplitWidth512x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 512
override lazy val depth = BigInt(512)
override lazy val memWidth = 8
override lazy val libWidth = 8
@@ -184,7 +184,7 @@ class SplitWidth512x8_rw extends MacroCompilerSpec with HasSRAMGenerator with Ha
// Try non-power of two widths against a base memory width of 8.
class SplitWidth1024x67_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 67
override lazy val libWidth = 8
@@ -192,7 +192,7 @@ class SplitWidth1024x67_rw extends MacroCompilerSpec with HasSRAMGenerator with
}
class SplitWidth1024x60_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 60
override lazy val libWidth = 8
@@ -200,7 +200,7 @@ class SplitWidth1024x60_rw extends MacroCompilerSpec with HasSRAMGenerator with
}
class SplitWidth1024x42_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 42
override lazy val libWidth = 8
@@ -208,7 +208,7 @@ class SplitWidth1024x42_rw extends MacroCompilerSpec with HasSRAMGenerator with
}
class SplitWidth1024x20_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 20
override lazy val libWidth = 8
@@ -216,7 +216,7 @@ class SplitWidth1024x20_rw extends MacroCompilerSpec with HasSRAMGenerator with
}
class SplitWidth1024x17_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 17
override lazy val libWidth = 8
@@ -224,7 +224,7 @@ class SplitWidth1024x17_rw extends MacroCompilerSpec with HasSRAMGenerator with
}
class SplitWidth1024x15_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 15
override lazy val libWidth = 8
@@ -232,7 +232,7 @@ class SplitWidth1024x15_rw extends MacroCompilerSpec with HasSRAMGenerator with
}
class SplitWidth1024x9_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 9
override lazy val libWidth = 8
@@ -241,7 +241,7 @@ class SplitWidth1024x9_rw extends MacroCompilerSpec with HasSRAMGenerator with H
// Try against a non-power of two base memory width.
class SplitWidth1024x64_mem11_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 64
override lazy val libWidth = 11
@@ -249,7 +249,7 @@ class SplitWidth1024x64_mem11_rw extends MacroCompilerSpec with HasSRAMGenerator
}
class SplitWidth1024x33_mem11_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 33
override lazy val libWidth = 11
@@ -257,7 +257,7 @@ class SplitWidth1024x33_mem11_rw extends MacroCompilerSpec with HasSRAMGenerator
}
class SplitWidth1024x16_mem11_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 16
override lazy val libWidth = 11
@@ -267,7 +267,7 @@ class SplitWidth1024x16_mem11_rw extends MacroCompilerSpec with HasSRAMGenerator
// Masked RAM
class SplitWidth1024x8_memGran_8_libGran_1_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 8
override lazy val libWidth = 8
override lazy val memMaskGran = Some(8)
@@ -277,7 +277,7 @@ class SplitWidth1024x8_memGran_8_libGran_1_rw extends MacroCompilerSpec with Has
}
class SplitWidth1024x16_memGran_8_libGran_1_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 16
override lazy val libWidth = 8
override lazy val memMaskGran = Some(8)
@@ -287,7 +287,7 @@ class SplitWidth1024x16_memGran_8_libGran_1_rw extends MacroCompilerSpec with Ha
}
class SplitWidth1024x16_memGran_8_libGran_8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 16
override lazy val libWidth = 8
override lazy val memMaskGran = Some(8)
@@ -297,7 +297,7 @@ class SplitWidth1024x16_memGran_8_libGran_8_rw extends MacroCompilerSpec with Ha
}
class SplitWidth1024x128_memGran_8_libGran_1_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 128
override lazy val libWidth = 32
override lazy val memMaskGran = Some(8)
@@ -307,7 +307,7 @@ class SplitWidth1024x128_memGran_8_libGran_1_rw extends MacroCompilerSpec with H
}
class SplitWidth1024x16_memGran_4_libGran_1_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 16
override lazy val libWidth = 8
override lazy val memMaskGran = Some(4)
@@ -317,7 +317,7 @@ class SplitWidth1024x16_memGran_4_libGran_1_rw extends MacroCompilerSpec with Ha
}
class SplitWidth1024x16_memGran_2_libGran_1_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 16
override lazy val libWidth = 8
override lazy val memMaskGran = Some(2)
@@ -327,7 +327,7 @@ class SplitWidth1024x16_memGran_2_libGran_1_rw extends MacroCompilerSpec with Ha
}
class SplitWidth1024x16_memGran_16_libGran_1_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 16
override lazy val libWidth = 8
override lazy val memMaskGran = Some(16)
@@ -339,7 +339,7 @@ class SplitWidth1024x16_memGran_16_libGran_1_rw extends MacroCompilerSpec with H
// Non-masked mem, masked lib
class SplitWidth1024x16_libGran_8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 16
override lazy val libWidth = 8
override lazy val libMaskGran = Some(8)
@@ -348,7 +348,7 @@ class SplitWidth1024x16_libGran_8_rw extends MacroCompilerSpec with HasSRAMGener
}
class SplitWidth1024x16_libGran_1_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 16
override lazy val libWidth = 8
override lazy val libMaskGran = Some(1)
@@ -359,7 +359,7 @@ class SplitWidth1024x16_libGran_1_rw extends MacroCompilerSpec with HasSRAMGener
// Non-memMask and non-1 libMask
class SplitWidth1024x16_memGran_8_libGran_2_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 16
override lazy val libWidth = 8
override lazy val memMaskGran = Some(8)
@@ -371,7 +371,7 @@ class SplitWidth1024x16_memGran_8_libGran_2_rw extends MacroCompilerSpec with Ha
// Non-power of two memGran
class SplitWidth1024x16_memGran_9_libGran_1_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 16
override lazy val libWidth = 8
override lazy val memMaskGran = Some(9)
@@ -387,7 +387,7 @@ class SplitWidth1024x16_memGran_9_libGran_1_rw extends MacroCompilerSpec with Ha
class SplitWidth1024x32_readEnable_Lib extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
import mdf.macrolib._
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 32
override lazy val libWidth = 8
@@ -445,7 +445,7 @@ class SplitWidth1024x32_readEnable_Lib extends MacroCompilerSpec with HasSRAMGen
class SplitWidth1024x32_readEnable_Mem extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
import mdf.macrolib._
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 32
override lazy val libWidth = 8
@@ -471,7 +471,7 @@ class SplitWidth1024x32_readEnable_Mem extends MacroCompilerSpec with HasSRAMGen
class SplitWidth1024x32_readEnable_LibMem extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
import mdf.macrolib._
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
override lazy val memWidth = 32
override lazy val libWidth = 8

38
macros/src/test/scala/SpecificExamples.scala
View File

@@ -9,8 +9,8 @@ import mdf.macrolib._
// TODO: check the actual verilog's correctness?
class GenerateSomeVerilog extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 32
override lazy val memDepth = 2048
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(2048)
override lazy val libDepth = BigInt(1024)
it should "execute fine" in {
compileExecuteAndTest(mem, lib, v, output)
@@ -35,7 +35,7 @@ class BOOMTest extends MacroCompilerSpec with HasSRAMGenerator {
"type" : "sram",
"name" : "_T_182_ext",
"width" : 88,
"depth" : 64,
"depth" : "64",
"ports" : [ {
"address port name" : "R0_addr",
"address port polarity" : "active high",
@@ -62,7 +62,7 @@ class BOOMTest extends MacroCompilerSpec with HasSRAMGenerator {
"type" : "sram",
"name" : "_T_84_ext",
"width" : 64,
"depth" : 512,
"depth" : "512",
"ports" : [ {
"address port name" : "R0_addr",
"address port polarity" : "active high",
@@ -89,7 +89,7 @@ class BOOMTest extends MacroCompilerSpec with HasSRAMGenerator {
"type" : "sram",
"name" : "tag_array_ext",
"width" : 80,
"depth" : 64,
"depth" : "64",
"ports" : [ {
"address port name" : "RW0_addr",
"address port polarity" : "active high",
@@ -111,7 +111,7 @@ class BOOMTest extends MacroCompilerSpec with HasSRAMGenerator {
"type" : "sram",
"name" : "_T_886_ext",
"width" : 64,
"depth" : 512,
"depth" : "512",
"ports" : [ {
"address port name" : "RW0_addr",
"address port polarity" : "active high",
@@ -130,7 +130,7 @@ class BOOMTest extends MacroCompilerSpec with HasSRAMGenerator {
"type" : "sram",
"name" : "entries_info_ext",
"width" : 40,
"depth" : 24,
"depth" : "24",
"ports" : [ {
"address port name" : "R0_addr",
"address port polarity" : "active high",
@@ -154,7 +154,7 @@ class BOOMTest extends MacroCompilerSpec with HasSRAMGenerator {
"type" : "sram",
"name" : "smem_ext",
"width" : 32,
"depth" : 32,
"depth" : "32",
"ports" : [ {
"address port name" : "RW0_addr",
"address port polarity" : "active high",
@@ -176,7 +176,7 @@ class BOOMTest extends MacroCompilerSpec with HasSRAMGenerator {
"type" : "sram",
"name" : "smem_0_ext",
"width" : 32,
"depth" : 64,
"depth" : "64",
"ports" : [ {
"address port name" : "RW0_addr",
"address port polarity" : "active high",
@@ -1197,12 +1197,12 @@ circuit smem_0_ext :
class SmallTagArrayTest extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleTestGenerator {
// Test that mapping a smaller memory using a larger lib can still work.
override def memWidth: Int = 26
override def memDepth: Int = 2
override def memDepth: BigInt = BigInt(2)
override def memMaskGran: Option[Int] = Some(26)
override def memPortPrefix: String = ""
override def libWidth: Int = 32
override def libDepth: Int = 64
override def libDepth: BigInt = BigInt(64)
override def libMaskGran: Option[Int] = Some(1)
override def libPortPrefix: String = ""
@@ -1239,7 +1239,7 @@ class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator {
width=8,
family="1rw",
ports=Seq(
generateReadWritePort("", 8, 1024)
generateReadWritePort("", 8, BigInt(1024))
)
),
SRAMMacro(
@@ -1248,7 +1248,7 @@ class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator {
width=32,
family="1rw",
ports=Seq(
generateReadWritePort("", 32, 512)
generateReadWritePort("", 32, BigInt(512))
)
),
SRAMMacro(
@@ -1257,7 +1257,7 @@ class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator {
width=128,
family="1rw",
ports=Seq(
generateReadWritePort("", 128, 64)
generateReadWritePort("", 128, BigInt(64))
)
),
SRAMMacro(
@@ -1266,7 +1266,7 @@ class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator {
width=32,
family="1rw",
ports=Seq(
generateReadWritePort("", 32, 64)
generateReadWritePort("", 32, BigInt(64))
)
),
SRAMMacro(
@@ -1275,7 +1275,7 @@ class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator {
width=8,
family="1rw",
ports=Seq(
generateReadWritePort("", 8, 64)
generateReadWritePort("", 8, BigInt(64))
)
),
SRAMMacro(
@@ -1284,7 +1284,7 @@ class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator {
width=8,
family="1rw",
ports=Seq(
generateReadWritePort("", 8, 512)
generateReadWritePort("", 8, BigInt(512))
)
),
SRAMMacro(
@@ -1293,8 +1293,8 @@ class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator {
width=32,
family="1r1w",
ports=Seq(
generateReadPort("portA", 32, 64),
generateWritePort("portB", 32, 64)
generateReadPort("portA", 32, BigInt(64)),
generateWritePort("portB", 32, BigInt(64))
)
)
)

168
macros/src/test/scala/SynFlops.scala
View File

@@ -6,6 +6,22 @@ trait HasSynFlopsTestGenerator extends HasSimpleTestGenerator {
this: MacroCompilerSpec with HasSRAMGenerator =>
def generateFlops: String = {
s"""
inst mem_0_0 of split_${lib_name}
mem_0_0.${libPortPrefix}_clk <= ${libPortPrefix}_clk
mem_0_0.${libPortPrefix}_addr <= ${libPortPrefix}_addr
node ${libPortPrefix}_dout_0_0 = bits(mem_0_0.${libPortPrefix}_dout, ${libWidth-1}, 0)
mem_0_0.${libPortPrefix}_din <= bits(${libPortPrefix}_din, ${libWidth-1}, 0)
mem_0_0.${libPortPrefix}_write_en <= and(and(${libPortPrefix}_write_en, UInt<1>("h1")), UInt<1>("h1"))
node ${libPortPrefix}_dout_0 = ${libPortPrefix}_dout_0_0
${libPortPrefix}_dout <= mux(UInt<1>("h1"), ${libPortPrefix}_dout_0, UInt<1>("h0"))
module split_${lib_name} :
input ${libPortPrefix}_addr : UInt<${lib_addr_width}>
input ${libPortPrefix}_clk : Clock
input ${libPortPrefix}_din : UInt<${libWidth}>
output ${libPortPrefix}_dout : UInt<${libWidth}>
input ${libPortPrefix}_write_en : UInt<1>
mem ram :
data-type => UInt<${libWidth}>
depth => ${libDepth}
@@ -17,9 +33,9 @@ s"""
ram.RW_0.addr <= ${libPortPrefix}_addr
ram.RW_0.en <= UInt<1>("h1")
ram.RW_0.wmode <= ${libPortPrefix}_write_en
ram.RW_0.wmask <= UInt<1>("h1")
${libPortPrefix}_dout <= ram.RW_0.rdata
ram.RW_0.wdata <= ${libPortPrefix}_din
ram.RW_0.wmask <= UInt<1>("h1")
"""
}
@@ -43,29 +59,29 @@ ${generateFlops}
}
class Synflops2048x8_noLib extends MacroCompilerSpec with HasSRAMGenerator with HasNoLibTestGenerator with HasSynFlopsTestGenerator {
override lazy val memDepth = 2048
override lazy val memDepth = BigInt(2048)
override lazy val memWidth = 8
compileExecuteAndTest(mem, None, v, output, true)
}
class Synflops2048x16_noLib extends MacroCompilerSpec with HasSRAMGenerator with HasNoLibTestGenerator with HasSynFlopsTestGenerator {
override lazy val memDepth = 2048
override lazy val memDepth = BigInt(2048)
override lazy val memWidth = 16
compileExecuteAndTest(mem, None, v, output, true)
}
class Synflops8192x16_noLib extends MacroCompilerSpec with HasSRAMGenerator with HasNoLibTestGenerator with HasSynFlopsTestGenerator {
override lazy val memDepth = 8192
override lazy val memDepth = BigInt(8192)
override lazy val memWidth = 16
compileExecuteAndTest(mem, None, v, output, true)
}
class Synflops2048x16_depth_Lib extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator with HasSynFlopsTestGenerator {
override lazy val memDepth = 2048
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(2048)
override lazy val libDepth = BigInt(1024)
override lazy val width = 16
compileExecuteAndTest(mem, lib, v, output, true)
@@ -74,7 +90,7 @@ class Synflops2048x16_depth_Lib extends MacroCompilerSpec with HasSRAMGenerator
class Synflops2048x64_width_Lib extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator with HasSynFlopsTestGenerator {
override lazy val memWidth = 64
override lazy val libWidth = 8
override lazy val depth = 1024
override lazy val depth = BigInt(1024)
compileExecuteAndTest(mem, lib, v, output, true)
}
@@ -82,8 +98,8 @@ class Synflops2048x64_width_Lib extends MacroCompilerSpec with HasSRAMGenerator
class Synflops_SplitPorts_Read_Write extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator with HasSynFlopsTestGenerator {
import mdf.macrolib._
override lazy val memDepth = 2048
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(2048)
override lazy val libDepth = BigInt(1024)
override lazy val width = 8
override def generateLibSRAM = SRAMMacro(
@@ -162,6 +178,26 @@ circuit target_memory :
override def generateFlops =
"""
inst mem_0_0 of split_awesome_lib_mem
mem_0_0.innerB_clk <= innerB_clk
mem_0_0.innerB_addr <= innerB_addr
mem_0_0.innerB_din <= bits(innerB_din, 7, 0)
mem_0_0.innerB_write_en <= and(and(innerB_write_en, UInt<1>("h1")), UInt<1>("h1"))
mem_0_0.innerA_clk <= innerA_clk
mem_0_0.innerA_addr <= innerA_addr
node innerA_dout_0_0 = bits(mem_0_0.innerA_dout, 7, 0)
node innerA_dout_0 = innerA_dout_0_0
innerA_dout <= mux(UInt<1>("h1"), innerA_dout_0, UInt<1>("h0"))
module split_awesome_lib_mem :
input innerA_addr : UInt<10>
input innerA_clk : Clock
output innerA_dout : UInt<8>
input innerB_addr : UInt<10>
input innerB_clk : Clock
input innerB_din : UInt<8>
input innerB_write_en : UInt<1>
mem ram :
data-type => UInt<8>
depth => 1024
@@ -177,8 +213,8 @@ circuit target_memory :
ram.W_0.clk <= innerB_clk
ram.W_0.addr <= innerB_addr
ram.W_0.en <= innerB_write_en
ram.W_0.data <= innerB_din
ram.W_0.mask <= UInt<1>("h1")
ram.W_0.data <= innerB_din
"""
"Non-masked split lib; split mem" should "syn flops fine" in {
@@ -189,8 +225,8 @@ circuit target_memory :
class Synflops_SplitPorts_MaskedMem_Read_MaskedWrite extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator with HasSynFlopsTestGenerator {
import mdf.macrolib._
override lazy val memDepth = 2048
override lazy val libDepth = 1024
override lazy val memDepth = BigInt(2048)
override lazy val libDepth = BigInt(1024)
override lazy val width = 8
override lazy val memMaskGran = Some(8)
override lazy val libMaskGran = Some(1)
@@ -275,8 +311,94 @@ circuit target_memory :
override def generateFlops =
"""
inst mem_0_0 of split_awesome_lib_mem
inst mem_0_1 of split_awesome_lib_mem
inst mem_0_2 of split_awesome_lib_mem
inst mem_0_3 of split_awesome_lib_mem
inst mem_0_4 of split_awesome_lib_mem
inst mem_0_5 of split_awesome_lib_mem
inst mem_0_6 of split_awesome_lib_mem
inst mem_0_7 of split_awesome_lib_mem
mem_0_0.innerB_clk <= innerB_clk
mem_0_0.innerB_addr <= innerB_addr
mem_0_0.innerB_din <= bits(innerB_din, 0, 0)
mem_0_0.innerB_mask <= bits(innerB_mask, 0, 0)
mem_0_0.innerB_write_en <= and(and(innerB_write_en, UInt<1>("h1")), UInt<1>("h1"))
mem_0_1.innerB_clk <= innerB_clk
mem_0_1.innerB_addr <= innerB_addr
mem_0_1.innerB_din <= bits(innerB_din, 1, 1)
mem_0_1.innerB_mask <= bits(innerB_mask, 1, 1)
mem_0_1.innerB_write_en <= and(and(innerB_write_en, UInt<1>("h1")), UInt<1>("h1"))
mem_0_2.innerB_clk <= innerB_clk
mem_0_2.innerB_addr <= innerB_addr
mem_0_2.innerB_din <= bits(innerB_din, 2, 2)
mem_0_2.innerB_mask <= bits(innerB_mask, 2, 2)
mem_0_2.innerB_write_en <= and(and(innerB_write_en, UInt<1>("h1")), UInt<1>("h1"))
mem_0_3.innerB_clk <= innerB_clk
mem_0_3.innerB_addr <= innerB_addr
mem_0_3.innerB_din <= bits(innerB_din, 3, 3)
mem_0_3.innerB_mask <= bits(innerB_mask, 3, 3)
mem_0_3.innerB_write_en <= and(and(innerB_write_en, UInt<1>("h1")), UInt<1>("h1"))
mem_0_4.innerB_clk <= innerB_clk
mem_0_4.innerB_addr <= innerB_addr
mem_0_4.innerB_din <= bits(innerB_din, 4, 4)
mem_0_4.innerB_mask <= bits(innerB_mask, 4, 4)
mem_0_4.innerB_write_en <= and(and(innerB_write_en, UInt<1>("h1")), UInt<1>("h1"))
mem_0_5.innerB_clk <= innerB_clk
mem_0_5.innerB_addr <= innerB_addr
mem_0_5.innerB_din <= bits(innerB_din, 5, 5)
mem_0_5.innerB_mask <= bits(innerB_mask, 5, 5)
mem_0_5.innerB_write_en <= and(and(innerB_write_en, UInt<1>("h1")), UInt<1>("h1"))
mem_0_6.innerB_clk <= innerB_clk
mem_0_6.innerB_addr <= innerB_addr
mem_0_6.innerB_din <= bits(innerB_din, 6, 6)
mem_0_6.innerB_mask <= bits(innerB_mask, 6, 6)
mem_0_6.innerB_write_en <= and(and(innerB_write_en, UInt<1>("h1")), UInt<1>("h1"))
mem_0_7.innerB_clk <= innerB_clk
mem_0_7.innerB_addr <= innerB_addr
mem_0_7.innerB_din <= bits(innerB_din, 7, 7)
mem_0_7.innerB_mask <= bits(innerB_mask, 7, 7)
mem_0_7.innerB_write_en <= and(and(innerB_write_en, UInt<1>("h1")), UInt<1>("h1"))
mem_0_0.innerA_clk <= innerA_clk
mem_0_0.innerA_addr <= innerA_addr
node innerA_dout_0_0 = bits(mem_0_0.innerA_dout, 0, 0)
mem_0_1.innerA_clk <= innerA_clk
mem_0_1.innerA_addr <= innerA_addr
node innerA_dout_0_1 = bits(mem_0_1.innerA_dout, 0, 0)
mem_0_2.innerA_clk <= innerA_clk
mem_0_2.innerA_addr <= innerA_addr
node innerA_dout_0_2 = bits(mem_0_2.innerA_dout, 0, 0)
mem_0_3.innerA_clk <= innerA_clk
mem_0_3.innerA_addr <= innerA_addr
node innerA_dout_0_3 = bits(mem_0_3.innerA_dout, 0, 0)
mem_0_4.innerA_clk <= innerA_clk
mem_0_4.innerA_addr <= innerA_addr
node innerA_dout_0_4 = bits(mem_0_4.innerA_dout, 0, 0)
mem_0_5.innerA_clk <= innerA_clk
mem_0_5.innerA_addr <= innerA_addr
node innerA_dout_0_5 = bits(mem_0_5.innerA_dout, 0, 0)
mem_0_6.innerA_clk <= innerA_clk
mem_0_6.innerA_addr <= innerA_addr
node innerA_dout_0_6 = bits(mem_0_6.innerA_dout, 0, 0)
mem_0_7.innerA_clk <= innerA_clk
mem_0_7.innerA_addr <= innerA_addr
node innerA_dout_0_7 = bits(mem_0_7.innerA_dout, 0, 0)
node innerA_dout_0 = cat(innerA_dout_0_7, cat(innerA_dout_0_6, cat(innerA_dout_0_5, cat(innerA_dout_0_4, cat(innerA_dout_0_3, cat(innerA_dout_0_2, cat(innerA_dout_0_1, innerA_dout_0_0)))))))
innerA_dout <= mux(UInt<1>("h1"), innerA_dout_0, UInt<1>("h0"))
module split_awesome_lib_mem :
input innerA_addr : UInt<10>
input innerA_clk : Clock
output innerA_dout : UInt<1>
input innerB_addr : UInt<10>
input innerB_clk : Clock
input innerB_din : UInt<1>
input innerB_write_en : UInt<1>
input innerB_mask : UInt<1>
mem ram :
data-type => UInt<1>[8]
data-type => UInt<1>
depth => 1024
read-latency => 1
write-latency => 1
@@ -286,26 +408,12 @@ circuit target_memory :
ram.R_0.clk <= innerA_clk
ram.R_0.addr <= innerA_addr
ram.R_0.en <= UInt<1>("h1")
innerA_dout <= cat(ram.R_0.data[7], cat(ram.R_0.data[6], cat(ram.R_0.data[5], cat(ram.R_0.data[4], cat(ram.R_0.data[3], cat(ram.R_0.data[2], cat(ram.R_0.data[1], ram.R_0.data[0])))))))
innerA_dout <= ram.R_0.data
ram.W_0.clk <= innerB_clk
ram.W_0.addr <= innerB_addr
ram.W_0.en <= innerB_write_en
ram.W_0.data[0] <= bits(innerB_din, 0, 0)
ram.W_0.data[1] <= bits(innerB_din, 1, 1)
ram.W_0.data[2] <= bits(innerB_din, 2, 2)
ram.W_0.data[3] <= bits(innerB_din, 3, 3)
ram.W_0.data[4] <= bits(innerB_din, 4, 4)
ram.W_0.data[5] <= bits(innerB_din, 5, 5)
ram.W_0.data[6] <= bits(innerB_din, 6, 6)
ram.W_0.data[7] <= bits(innerB_din, 7, 7)
ram.W_0.mask[0] <= bits(innerB_mask, 0, 0)
ram.W_0.mask[1] <= bits(innerB_mask, 1, 1)
ram.W_0.mask[2] <= bits(innerB_mask, 2, 2)
ram.W_0.mask[3] <= bits(innerB_mask, 3, 3)
ram.W_0.mask[4] <= bits(innerB_mask, 4, 4)
ram.W_0.mask[5] <= bits(innerB_mask, 5, 5)
ram.W_0.mask[6] <= bits(innerB_mask, 6, 6)
ram.W_0.mask[7] <= bits(innerB_mask, 7, 7)
ram.W_0.mask <= innerB_mask
ram.W_0.data <= innerB_din
"""
"masked split lib; masked split mem" should "syn flops fine" in {