542 lines
19 KiB
Scala
542 lines
19 KiB
Scala
package barstools.macros
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// Test the width splitting aspect of the memory compiler.
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// For example, implementing a 1024x32 memory using four 1024x8 memories.
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trait HasSimpleWidthTestGenerator extends HasSimpleTestGenerator {
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this: MacroCompilerSpec with HasSRAMGenerator =>
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def depth: BigInt
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override lazy val memDepth = depth
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override lazy val libDepth = depth
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override def generateBody(): String = {
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val output = new StringBuilder
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// Generate mem_0_<i> lines for number of width instances.
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output.append(
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((0 to widthInstances - 1) map {i:Int => s"""
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inst mem_0_${i} of ${lib_name}
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"""
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}).reduceLeft(_ + _)
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)
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// Generate submemory connection blocks.
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output append (for (i <- 0 to widthInstances - 1) yield {
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// Width of this submemory.
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val myMemWidth = if (i == widthInstances - 1) lastWidthBits else usableLibWidth
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// Base bit of this submemory.
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// e.g. if libWidth is 8 and this is submemory 2 (0-indexed), then this
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// would be 16.
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val myBaseBit = usableLibWidth*i
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val maskStatement = generateMaskStatement(i, 0)
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// We need to use writeEnable as a crude "mask" if mem has a mask but
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// lib does not.
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val writeEnableBit = if (libMaskGran.isEmpty && memMaskGran.isDefined) {
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val outerMaskBit = myBaseBit / memMaskGran.get
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s"bits(outer_mask, ${outerMaskBit}, ${outerMaskBit})"
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} else """UInt<1>("h1")"""
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s"""
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mem_0_${i}.${libPortPrefix}_clk <= ${memPortPrefix}_clk
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mem_0_${i}.${libPortPrefix}_addr <= ${memPortPrefix}_addr
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node ${memPortPrefix}_dout_0_${i} = bits(mem_0_${i}.${libPortPrefix}_dout, ${myMemWidth - 1}, 0)
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mem_0_${i}.${libPortPrefix}_din <= bits(${memPortPrefix}_din, ${myBaseBit + myMemWidth - 1}, ${myBaseBit})
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${maskStatement}
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mem_0_${i}.${libPortPrefix}_write_en <= and(and(${memPortPrefix}_write_en, ${writeEnableBit}), UInt<1>("h1"))
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"""
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}).reduceLeft(_ + _)
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// Generate final output that concats together the sub-memories.
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// e.g. cat(outer_dout_0_2, cat(outer_dout_0_1, outer_dout_0_0))
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output append {
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val doutStatements = ((widthInstances - 1 to 0 by -1) map (i => s"${memPortPrefix}_dout_0_${i}"))
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val catStmt = doutStatements.init.foldRight(doutStatements.last)((l: String, r: String) => s"cat($l, $r)")
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s"""
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node ${memPortPrefix}_dout_0 = ${catStmt}
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"""
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}
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output append
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s"""
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${memPortPrefix}_dout <= mux(UInt<1>("h1"), ${memPortPrefix}_dout_0, UInt<1>("h0"))
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"""
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output.toString
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}
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}
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// Try different widths against a base memory width of 8.
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class SplitWidth1024x128_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 128
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override lazy val libWidth = 8
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth1024x64_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 64
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override lazy val libWidth = 8
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth1024x32_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 32
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override lazy val libWidth = 8
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth1024x16_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 16
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override lazy val libWidth = 8
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth1024x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 8
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override lazy val libWidth = 8
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compileExecuteAndTest(mem, lib, v, output)
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}
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// Try different widths against a base memory width of 16.
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class SplitWidth1024x128_lib16_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 128
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override lazy val libWidth = 16
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth1024x64_lib16_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 64
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override lazy val libWidth = 16
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth1024x32_lib16_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 32
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override lazy val libWidth = 16
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth1024x16_lib16_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 16
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override lazy val libWidth = 16
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compileExecuteAndTest(mem, lib, v, output)
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}
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// Try different widths against a base memory width of 8 but depth 512 instead of 1024.
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class SplitWidth512x128_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(512)
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override lazy val memWidth = 128
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override lazy val libWidth = 8
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth512x64_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(512)
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override lazy val memWidth = 64
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override lazy val libWidth = 8
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth512x32_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(512)
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override lazy val memWidth = 32
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override lazy val libWidth = 8
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth512x16_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(512)
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override lazy val memWidth = 16
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override lazy val libWidth = 8
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth512x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(512)
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override lazy val memWidth = 8
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override lazy val libWidth = 8
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compileExecuteAndTest(mem, lib, v, output)
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}
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// Try non-power of two widths against a base memory width of 8.
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class SplitWidth1024x67_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 67
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override lazy val libWidth = 8
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth1024x60_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 60
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override lazy val libWidth = 8
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth1024x42_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 42
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override lazy val libWidth = 8
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth1024x20_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 20
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override lazy val libWidth = 8
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth1024x17_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 17
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override lazy val libWidth = 8
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth1024x15_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 15
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override lazy val libWidth = 8
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth1024x9_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 9
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override lazy val libWidth = 8
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compileExecuteAndTest(mem, lib, v, output)
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}
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// Try against a non-power of two base memory width.
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class SplitWidth1024x64_mem11_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 64
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override lazy val libWidth = 11
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth1024x33_mem11_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 33
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override lazy val libWidth = 11
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth1024x16_mem11_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 16
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override lazy val libWidth = 11
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compileExecuteAndTest(mem, lib, v, output)
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}
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// Masked RAM
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class SplitWidth1024x8_memGran_8_libGran_1_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 8
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override lazy val libWidth = 8
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override lazy val memMaskGran = Some(8)
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override lazy val libMaskGran = Some(1)
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth1024x16_memGran_8_libGran_1_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 16
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override lazy val libWidth = 8
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override lazy val memMaskGran = Some(8)
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override lazy val libMaskGran = Some(1)
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth1024x16_memGran_8_libGran_8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 16
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override lazy val libWidth = 8
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override lazy val memMaskGran = Some(8)
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override lazy val libMaskGran = Some(8)
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth1024x128_memGran_8_libGran_1_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 128
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override lazy val libWidth = 32
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override lazy val memMaskGran = Some(8)
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override lazy val libMaskGran = Some(1)
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth1024x16_memGran_4_libGran_1_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 16
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override lazy val libWidth = 8
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override lazy val memMaskGran = Some(4)
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override lazy val libMaskGran = Some(1)
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth1024x16_memGran_2_libGran_1_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 16
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override lazy val libWidth = 8
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override lazy val memMaskGran = Some(2)
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override lazy val libMaskGran = Some(1)
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth1024x16_memGran_16_libGran_1_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 16
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override lazy val libWidth = 8
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override lazy val memMaskGran = Some(16)
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override lazy val libMaskGran = Some(1)
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compileExecuteAndTest(mem, lib, v, output)
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}
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// Non-masked mem, masked lib
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class SplitWidth1024x16_libGran_8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 16
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override lazy val libWidth = 8
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override lazy val libMaskGran = Some(8)
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth1024x16_libGran_1_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 16
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override lazy val libWidth = 8
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override lazy val libMaskGran = Some(1)
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compileExecuteAndTest(mem, lib, v, output)
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}
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// Non-memMask and non-1 libMask
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class SplitWidth1024x16_memGran_8_libGran_2_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 16
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override lazy val libWidth = 8
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override lazy val memMaskGran = Some(8)
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override lazy val libMaskGran = Some(2)
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compileExecuteAndTest(mem, lib, v, output)
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}
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// Non-power of two memGran
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class SplitWidth1024x16_memGran_9_libGran_1_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 16
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override lazy val libWidth = 8
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override lazy val memMaskGran = Some(9)
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override lazy val libMaskGran = Some(1)
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it should "be enabled when non-power of two masks are supported" is (pending)
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//~ compile(mem, lib, v, false)
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//~ execute(mem, lib, false, output)
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}
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// Read enable
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class SplitWidth1024x32_readEnable_Lib extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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import mdf.macrolib._
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 32
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override lazy val libWidth = 8
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override def generateLibSRAM() = {
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SRAMMacro(
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name=lib_name,
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width=libWidth,
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depth=libDepth,
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family="1rw",
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ports=Seq(generateTestPort(
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"lib", Some(libWidth), Some(libDepth), maskGran=libMaskGran,
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write=true, writeEnable=true,
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read=true, readEnable=true
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))
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)
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}
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override def generateBody() =
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"""
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inst mem_0_0 of awesome_lib_mem
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inst mem_0_1 of awesome_lib_mem
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inst mem_0_2 of awesome_lib_mem
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inst mem_0_3 of awesome_lib_mem
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mem_0_0.lib_clk <= outer_clk
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mem_0_0.lib_addr <= outer_addr
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node outer_dout_0_0 = bits(mem_0_0.lib_dout, 7, 0)
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mem_0_0.lib_din <= bits(outer_din, 7, 0)
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mem_0_0.lib_read_en <= and(not(outer_write_en), UInt<1>("h1"))
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mem_0_0.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1"))
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mem_0_1.lib_clk <= outer_clk
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mem_0_1.lib_addr <= outer_addr
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node outer_dout_0_1 = bits(mem_0_1.lib_dout, 7, 0)
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mem_0_1.lib_din <= bits(outer_din, 15, 8)
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mem_0_1.lib_read_en <= and(not(outer_write_en), UInt<1>("h1"))
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mem_0_1.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1"))
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mem_0_2.lib_clk <= outer_clk
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mem_0_2.lib_addr <= outer_addr
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node outer_dout_0_2 = bits(mem_0_2.lib_dout, 7, 0)
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mem_0_2.lib_din <= bits(outer_din, 23, 16)
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mem_0_2.lib_read_en <= and(not(outer_write_en), UInt<1>("h1"))
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mem_0_2.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1"))
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mem_0_3.lib_clk <= outer_clk
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mem_0_3.lib_addr <= outer_addr
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node outer_dout_0_3 = bits(mem_0_3.lib_dout, 7, 0)
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mem_0_3.lib_din <= bits(outer_din, 31, 24)
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mem_0_3.lib_read_en <= and(not(outer_write_en), UInt<1>("h1"))
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mem_0_3.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1"))
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node outer_dout_0 = cat(outer_dout_0_3, cat(outer_dout_0_2, cat(outer_dout_0_1, outer_dout_0_0)))
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outer_dout <= mux(UInt<1>("h1"), outer_dout_0, UInt<1>("h0"))
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"""
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth1024x32_readEnable_Mem extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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import mdf.macrolib._
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 32
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override lazy val libWidth = 8
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override def generateMemSRAM() = {
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SRAMMacro(
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name=mem_name,
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width=memWidth,
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depth=memDepth,
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family="1rw",
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ports=Seq(generateTestPort(
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"outer", Some(memWidth), Some(memDepth), maskGran=memMaskGran,
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write=true, writeEnable=true,
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read=true, readEnable=true
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))
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)
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}
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// No need to override body here due to the lack of a readEnable in the lib.
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compileExecuteAndTest(mem, lib, v, output)
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}
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class SplitWidth1024x32_readEnable_LibMem extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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import mdf.macrolib._
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override lazy val depth = BigInt(1024)
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override lazy val memWidth = 32
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override lazy val libWidth = 8
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override def generateLibSRAM() = {
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SRAMMacro(
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name=lib_name,
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width=libWidth,
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depth=libDepth,
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family="1rw",
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ports=Seq(generateTestPort(
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"lib", Some(libWidth), Some(libDepth), maskGran=libMaskGran,
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write=true, writeEnable=true,
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read=true, readEnable=true
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))
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)
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}
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override def generateMemSRAM() = {
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SRAMMacro(
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name=mem_name,
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width=memWidth,
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depth=memDepth,
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family="1rw",
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ports=Seq(generateTestPort(
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"outer", Some(memWidth), Some(memDepth), maskGran=memMaskGran,
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write=true, writeEnable=true,
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read=true, readEnable=true
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|
))
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)
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}
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|
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override def generateBody() =
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"""
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inst mem_0_0 of awesome_lib_mem
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inst mem_0_1 of awesome_lib_mem
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inst mem_0_2 of awesome_lib_mem
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inst mem_0_3 of awesome_lib_mem
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mem_0_0.lib_clk <= outer_clk
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mem_0_0.lib_addr <= outer_addr
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node outer_dout_0_0 = bits(mem_0_0.lib_dout, 7, 0)
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mem_0_0.lib_din <= bits(outer_din, 7, 0)
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mem_0_0.lib_read_en <= and(outer_read_en, UInt<1>("h1"))
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mem_0_0.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1"))
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mem_0_1.lib_clk <= outer_clk
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mem_0_1.lib_addr <= outer_addr
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node outer_dout_0_1 = bits(mem_0_1.lib_dout, 7, 0)
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mem_0_1.lib_din <= bits(outer_din, 15, 8)
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mem_0_1.lib_read_en <= and(outer_read_en, UInt<1>("h1"))
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mem_0_1.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1"))
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|
mem_0_2.lib_clk <= outer_clk
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|
mem_0_2.lib_addr <= outer_addr
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|
node outer_dout_0_2 = bits(mem_0_2.lib_dout, 7, 0)
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|
mem_0_2.lib_din <= bits(outer_din, 23, 16)
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|
mem_0_2.lib_read_en <= and(outer_read_en, UInt<1>("h1"))
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mem_0_2.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1"))
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|
mem_0_3.lib_clk <= outer_clk
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mem_0_3.lib_addr <= outer_addr
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|
node outer_dout_0_3 = bits(mem_0_3.lib_dout, 7, 0)
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mem_0_3.lib_din <= bits(outer_din, 31, 24)
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mem_0_3.lib_read_en <= and(outer_read_en, UInt<1>("h1"))
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mem_0_3.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1"))
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|
node outer_dout_0 = cat(outer_dout_0_3, cat(outer_dout_0_2, cat(outer_dout_0_1, outer_dout_0_0)))
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|
outer_dout <= mux(UInt<1>("h1"), outer_dout_0, UInt<1>("h0"))
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|
"""
|
|
|
|
compileExecuteAndTest(mem, lib, v, output)
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|
}
|