116 lines
3.3 KiB
Scala
116 lines
3.3 KiB
Scala
package barstools.macros
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import mdf.macrolib._
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/** Tests to check that the cost function mechanism is working properly. */
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/**
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* A test metric that simply favours memories with smaller widths, to test that
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* the metric is chosen properly.
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*/
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object TestMinWidthMetric extends CostMetric with CostMetricCompanion {
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// Smaller width = lower cost = favoured
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override def cost(mem: Macro, lib: Macro): Option[Double] = Some(lib.src.width)
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override def commandLineParams = Map()
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override def name = "TestMinWidthMetric"
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override def construct(m: Map[String, String]) = TestMinWidthMetric
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}
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/** Test that cost metric selection is working. */
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class SelectCostMetric extends MacroCompilerSpec with HasSRAMGenerator {
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val mem = s"mem-SelectCostMetric.json"
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val lib = s"lib-SelectCostMetric.json"
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val v = s"SelectCostMetric.v"
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// Cost metrics must be registered for them to work with the command line.
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CostMetric.registerCostMetric(TestMinWidthMetric)
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override val costMetric = Some(TestMinWidthMetric)
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val libSRAMs = Seq(
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SRAMMacro(
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name="SRAM_WIDTH_128",
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depth=BigInt(1024),
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width=128,
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family="1rw",
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ports=Seq(
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generateReadWritePort("", 128, BigInt(1024))
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)
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),
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SRAMMacro(
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name="SRAM_WIDTH_64",
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depth=BigInt(1024),
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width=64,
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family="1rw",
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ports=Seq(
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generateReadWritePort("", 64, BigInt(1024))
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)
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),
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SRAMMacro(
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name="SRAM_WIDTH_32",
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depth=BigInt(1024),
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width=32,
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family="1rw",
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ports=Seq(
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generateReadWritePort("", 32, BigInt(1024))
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)
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)
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)
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val memSRAMs = Seq(generateSRAM("target_memory", "", 128, BigInt(1024)))
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writeToLib(lib, libSRAMs)
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writeToMem(mem, memSRAMs)
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// Check that the min width SRAM was chosen, even though it is less efficient.
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val output =
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"""
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circuit target_memory :
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module target_memory :
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input addr : UInt<10>
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input clk : Clock
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input din : UInt<128>
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output dout : UInt<128>
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input write_en : UInt<1>
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inst mem_0_0 of SRAM_WIDTH_32
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inst mem_0_1 of SRAM_WIDTH_32
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inst mem_0_2 of SRAM_WIDTH_32
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inst mem_0_3 of SRAM_WIDTH_32
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mem_0_0.clk <= clk
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mem_0_0.addr <= addr
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node dout_0_0 = bits(mem_0_0.dout, 31, 0)
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mem_0_0.din <= bits(din, 31, 0)
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mem_0_0.write_en <= and(and(write_en, UInt<1>("h1")), UInt<1>("h1"))
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mem_0_1.clk <= clk
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mem_0_1.addr <= addr
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node dout_0_1 = bits(mem_0_1.dout, 31, 0)
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mem_0_1.din <= bits(din, 63, 32)
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mem_0_1.write_en <= and(and(write_en, UInt<1>("h1")), UInt<1>("h1"))
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mem_0_2.clk <= clk
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mem_0_2.addr <= addr
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node dout_0_2 = bits(mem_0_2.dout, 31, 0)
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mem_0_2.din <= bits(din, 95, 64)
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mem_0_2.write_en <= and(and(write_en, UInt<1>("h1")), UInt<1>("h1"))
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mem_0_3.clk <= clk
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mem_0_3.addr <= addr
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node dout_0_3 = bits(mem_0_3.dout, 31, 0)
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mem_0_3.din <= bits(din, 127, 96)
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mem_0_3.write_en <= and(and(write_en, UInt<1>("h1")), UInt<1>("h1"))
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node dout_0 = cat(dout_0_3, cat(dout_0_2, cat(dout_0_1, dout_0_0)))
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dout <= mux(UInt<1>("h1"), dout_0, UInt<1>("h0"))
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extmodule SRAM_WIDTH_32 :
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input addr : UInt<10>
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input clk : Clock
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input din : UInt<32>
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output dout : UInt<32>
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input write_en : UInt<1>
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defname = SRAM_WIDTH_32
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"""
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compileExecuteAndTest(mem, lib, v, output)
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}
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