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Forgot to update the verilog modules

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This commit is contained in:
John Wright
2020-03-30 13:50:27 -07:00
parent 62df79934e
commit bc3f8a42b3
1 changed files with 4 additions and 4 deletions
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8
iocell/src/main/resources/barstools/iocell/vsrc/IOCell.v
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@@ -2,7 +2,7 @@
`timescale 1ns/1ps `timescale 1ns/1ps
module ExampleAnalogIOCell( module GenericAnalogIOCell(
inout pad, inout pad,
inout core inout core
); );
@@ -12,7 +12,7 @@ module ExampleAnalogIOCell(
endmodule endmodule
module ExampleDigitalGPIOCell( module GenericDigitalGPIOCell(
inout pad, inout pad,
output i, output i,
input ie, input ie,
@@ -25,7 +25,7 @@ module ExampleDigitalGPIOCell(
endmodule endmodule
module ExampleDigitalInIOCell( module GenericDigitalInIOCell(
input pad, input pad,
output i, output i,
input ie input ie
@@ -35,7 +35,7 @@ module ExampleDigitalInIOCell(
endmodule endmodule
module ExampleDigitalOutIOCell( module GenericDigitalOutIOCell(
output pad, output pad,
input o, input o,
output oe output oe