From bc3f8a42b30801ae35b96b5792b1aacbb883fd2d Mon Sep 17 00:00:00 2001
From: John Wright <johnwright@eecs.berkeley.edu>
Date: Mon, 30 Mar 2020 13:50:27 -0700
Subject: [PATCH] Forgot to update the verilog modules

---
 iocell/src/main/resources/barstools/iocell/vsrc/IOCell.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/iocell/src/main/resources/barstools/iocell/vsrc/IOCell.v b/iocell/src/main/resources/barstools/iocell/vsrc/IOCell.v
index d0be6b0b..b3ee47ce 100644
--- a/iocell/src/main/resources/barstools/iocell/vsrc/IOCell.v
+++ b/iocell/src/main/resources/barstools/iocell/vsrc/IOCell.v
@@ -2,7 +2,7 @@
 
 `timescale 1ns/1ps
 
-module ExampleAnalogIOCell(
+module GenericAnalogIOCell(
     inout pad,
     inout core
 );
@@ -12,7 +12,7 @@ module ExampleAnalogIOCell(
 
 endmodule
 
-module ExampleDigitalGPIOCell(
+module GenericDigitalGPIOCell(
     inout pad,
     output i,
     input ie,
@@ -25,7 +25,7 @@ module ExampleDigitalGPIOCell(
 
 endmodule
 
-module ExampleDigitalInIOCell(
+module GenericDigitalInIOCell(
     input pad,
     output i,
     input ie
@@ -35,7 +35,7 @@ module ExampleDigitalInIOCell(
 
 endmodule
 
-module ExampleDigitalOutIOCell(
+module GenericDigitalOutIOCell(
     output pad,
     input o,
     output oe