From ad9ea333d1dfa8f6cef4da5401eb086a42dffb94 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 10 Apr 2023 15:35:53 -0700 Subject: [PATCH] Bump TestChipIp to improve default serial_tl behavior --- generators/chipyard/src/main/scala/config/ChipConfigs.scala | 1 - generators/testchipip | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index fa08acf7..2d6cb206 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -39,7 +39,6 @@ class ChipLikeQuadRocketConfig extends Config( new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS - new testchipip.WithSerialTLAsyncResetQueue ++ // Add Async reset queue to block ready while in reset new chipyard.config.AbstractConfig) diff --git a/generators/testchipip b/generators/testchipip index aa9170af..0d943d04 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit aa9170afe133e74e1c66b0082dc943e272d9e6f0 +Subproject commit 0d943d04b5510a3ee86f5145db6a4de80987bc5e