Update stage to use Dependency instead of classof
This commit is contained in:
@@ -10,27 +10,27 @@ import firrtl.stage.FirrtlCli
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import freechips.rocketchip.stage.RocketChipCli
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import freechips.rocketchip.stage.RocketChipCli
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import freechips.rocketchip.system.RocketChipStage
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import freechips.rocketchip.system.RocketChipStage
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import firrtl.options.{Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain}
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import firrtl.options.{Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain, Dependency}
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import firrtl.options.phases.DeletedWrapper
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import firrtl.options.phases.DeletedWrapper
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class ChipyardStage extends ChiselStage with PreservesAll[Phase] {
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class ChipyardStage extends ChiselStage with PreservesAll[Phase] {
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override val shell = new Shell("chipyard") with ChipyardCli with RocketChipCli with ChiselCli with FirrtlCli
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override val shell = new Shell("chipyard") with ChipyardCli with RocketChipCli with ChiselCli with FirrtlCli
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override val targets: Seq[PhaseDependency] = Seq(
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override val targets: Seq[PhaseDependency] = Seq(
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classOf[freechips.rocketchip.stage.phases.Checks],
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Dependency[freechips.rocketchip.stage.phases.Checks],
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classOf[freechips.rocketchip.stage.phases.TransformAnnotations],
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Dependency[freechips.rocketchip.stage.phases.TransformAnnotations],
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classOf[freechips.rocketchip.stage.phases.PreElaboration],
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Dependency[freechips.rocketchip.stage.phases.PreElaboration],
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classOf[chisel3.stage.phases.Checks],
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Dependency[chisel3.stage.phases.Checks],
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classOf[chisel3.stage.phases.Elaborate],
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Dependency[chisel3.stage.phases.Elaborate],
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classOf[freechips.rocketchip.stage.phases.GenerateROMs],
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Dependency[freechips.rocketchip.stage.phases.GenerateROMs],
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classOf[chisel3.stage.phases.AddImplicitOutputFile],
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Dependency[chisel3.stage.phases.AddImplicitOutputFile],
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classOf[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
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Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
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classOf[chisel3.stage.phases.MaybeAspectPhase],
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Dependency[chisel3.stage.phases.MaybeAspectPhase],
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classOf[chisel3.stage.phases.Emitter],
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Dependency[chisel3.stage.phases.Emitter],
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classOf[chisel3.stage.phases.Convert],
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Dependency[chisel3.stage.phases.Convert],
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classOf[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],
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Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],
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classOf[freechips.rocketchip.stage.phases.AddDefaultTests],
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Dependency[freechips.rocketchip.stage.phases.AddDefaultTests],
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classOf[chipyard.stage.phases.AddDefaultTests],
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Dependency[chipyard.stage.phases.AddDefaultTests],
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classOf[chipyard.stage.phases.GenerateTestSuiteMakefrags],
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Dependency[chipyard.stage.phases.GenerateTestSuiteMakefrags],
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classOf[freechips.rocketchip.stage.phases.GenerateArtefacts],
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Dependency[freechips.rocketchip.stage.phases.GenerateArtefacts],
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)
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)
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}
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}
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@@ -10,7 +10,7 @@ import chipsalliance.rocketchip.config.Parameters
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import chisel3.stage.phases.Elaborate
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import chisel3.stage.phases.Elaborate
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import firrtl.AnnotationSeq
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import firrtl.AnnotationSeq
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import firrtl.annotations.{Annotation, NoTargetAnnotation}
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import firrtl.annotations.{Annotation, NoTargetAnnotation}
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import firrtl.options.{Phase, PreservesAll}
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import firrtl.options.{Phase, PreservesAll, Dependency}
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import firrtl.options.Viewer.view
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import firrtl.options.Viewer.view
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import freechips.rocketchip.stage.RocketChipOptions
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import freechips.rocketchip.stage.RocketChipOptions
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import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation}
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import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation}
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@@ -23,9 +23,9 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS
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// Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase
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// Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase
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// because the RocketTestSuiteAnnotation is not serializable (but is not marked as such).
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// because the RocketTestSuiteAnnotation is not serializable (but is not marked as such).
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override val prerequisites = Seq(
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override val prerequisites = Seq(
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classOf[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],
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Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],
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classOf[freechips.rocketchip.stage.phases.AddDefaultTests])
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Dependency[freechips.rocketchip.stage.phases.AddDefaultTests])
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override val dependents = Seq(classOf[freechips.rocketchip.stage.phases.GenerateTestSuiteMakefrags])
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override val dependents = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateTestSuiteMakefrags])
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private def addTestSuiteAnnotations(implicit p: Parameters): Seq[Annotation] = {
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private def addTestSuiteAnnotations(implicit p: Parameters): Seq[Annotation] = {
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val annotations = mutable.ArrayBuffer[Annotation]()
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val annotations = mutable.ArrayBuffer[Annotation]()
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@@ -7,7 +7,7 @@ import scala.collection.mutable
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import firrtl.AnnotationSeq
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import firrtl.AnnotationSeq
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import firrtl.annotations.{Annotation, NoTargetAnnotation}
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import firrtl.annotations.{Annotation, NoTargetAnnotation}
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import firrtl.options.{Phase, PreservesAll, StageOptions, Unserializable}
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import firrtl.options.{Phase, PreservesAll, StageOptions, Unserializable, Dependency}
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import firrtl.options.Viewer.view
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import firrtl.options.Viewer.view
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import freechips.rocketchip.stage.RocketChipOptions
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import freechips.rocketchip.stage.RocketChipOptions
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import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation}
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import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation}
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@@ -24,8 +24,8 @@ case class CustomMakefragSnippet(val toMakefrag: String) extends NoTargetAnnotat
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class GenerateTestSuiteMakefrags extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils {
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class GenerateTestSuiteMakefrags extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils {
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// Our annotations tend not to be serializable, but are not marked as such.
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// Our annotations tend not to be serializable, but are not marked as such.
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override val prerequisites = Seq(classOf[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],
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override val prerequisites = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],
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classOf[chipyard.stage.phases.AddDefaultTests])
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Dependency[chipyard.stage.phases.AddDefaultTests])
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override def transform(annotations: AnnotationSeq): AnnotationSeq = {
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override def transform(annotations: AnnotationSeq): AnnotationSeq = {
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val targetDir = view[StageOptions](annotations).targetDir
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val targetDir = view[StageOptions](annotations).targetDir
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