From a255417513180ab4e4f53ee20b964e9eac701674 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Tue, 5 May 2020 15:24:51 -0700 Subject: [PATCH] Update stage to use Dependency instead of classof --- .../src/main/scala/stage/ChipyardStage.scala | 34 +++++++++---------- .../scala/stage/phases/AddDefaultTests.scala | 8 ++--- .../phases/GenerateTestSuiteMakefrags.scala | 6 ++-- 3 files changed, 24 insertions(+), 24 deletions(-) diff --git a/generators/chipyard/src/main/scala/stage/ChipyardStage.scala b/generators/chipyard/src/main/scala/stage/ChipyardStage.scala index a24afd43..4e429618 100644 --- a/generators/chipyard/src/main/scala/stage/ChipyardStage.scala +++ b/generators/chipyard/src/main/scala/stage/ChipyardStage.scala @@ -10,27 +10,27 @@ import firrtl.stage.FirrtlCli import freechips.rocketchip.stage.RocketChipCli import freechips.rocketchip.system.RocketChipStage -import firrtl.options.{Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain} +import firrtl.options.{Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain, Dependency} import firrtl.options.phases.DeletedWrapper class ChipyardStage extends ChiselStage with PreservesAll[Phase] { override val shell = new Shell("chipyard") with ChipyardCli with RocketChipCli with ChiselCli with FirrtlCli override val targets: Seq[PhaseDependency] = Seq( - classOf[freechips.rocketchip.stage.phases.Checks], - classOf[freechips.rocketchip.stage.phases.TransformAnnotations], - classOf[freechips.rocketchip.stage.phases.PreElaboration], - classOf[chisel3.stage.phases.Checks], - classOf[chisel3.stage.phases.Elaborate], - classOf[freechips.rocketchip.stage.phases.GenerateROMs], - classOf[chisel3.stage.phases.AddImplicitOutputFile], - classOf[chisel3.stage.phases.AddImplicitOutputAnnotationFile], - classOf[chisel3.stage.phases.MaybeAspectPhase], - classOf[chisel3.stage.phases.Emitter], - classOf[chisel3.stage.phases.Convert], - classOf[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], - classOf[freechips.rocketchip.stage.phases.AddDefaultTests], - classOf[chipyard.stage.phases.AddDefaultTests], - classOf[chipyard.stage.phases.GenerateTestSuiteMakefrags], - classOf[freechips.rocketchip.stage.phases.GenerateArtefacts], + Dependency[freechips.rocketchip.stage.phases.Checks], + Dependency[freechips.rocketchip.stage.phases.TransformAnnotations], + Dependency[freechips.rocketchip.stage.phases.PreElaboration], + Dependency[chisel3.stage.phases.Checks], + Dependency[chisel3.stage.phases.Elaborate], + Dependency[freechips.rocketchip.stage.phases.GenerateROMs], + Dependency[chisel3.stage.phases.AddImplicitOutputFile], + Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile], + Dependency[chisel3.stage.phases.MaybeAspectPhase], + Dependency[chisel3.stage.phases.Emitter], + Dependency[chisel3.stage.phases.Convert], + Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], + Dependency[freechips.rocketchip.stage.phases.AddDefaultTests], + Dependency[chipyard.stage.phases.AddDefaultTests], + Dependency[chipyard.stage.phases.GenerateTestSuiteMakefrags], + Dependency[freechips.rocketchip.stage.phases.GenerateArtefacts], ) } diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala index 277d04b5..fce5d432 100644 --- a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala +++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala @@ -10,7 +10,7 @@ import chipsalliance.rocketchip.config.Parameters import chisel3.stage.phases.Elaborate import firrtl.AnnotationSeq import firrtl.annotations.{Annotation, NoTargetAnnotation} -import firrtl.options.{Phase, PreservesAll} +import firrtl.options.{Phase, PreservesAll, Dependency} import firrtl.options.Viewer.view import freechips.rocketchip.stage.RocketChipOptions import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation} @@ -23,9 +23,9 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS // Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase // because the RocketTestSuiteAnnotation is not serializable (but is not marked as such). override val prerequisites = Seq( - classOf[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], - classOf[freechips.rocketchip.stage.phases.AddDefaultTests]) - override val dependents = Seq(classOf[freechips.rocketchip.stage.phases.GenerateTestSuiteMakefrags]) + Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], + Dependency[freechips.rocketchip.stage.phases.AddDefaultTests]) + override val dependents = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateTestSuiteMakefrags]) private def addTestSuiteAnnotations(implicit p: Parameters): Seq[Annotation] = { val annotations = mutable.ArrayBuffer[Annotation]() diff --git a/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala b/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala index 76f99ab7..0ed5ec11 100644 --- a/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala +++ b/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala @@ -7,7 +7,7 @@ import scala.collection.mutable import firrtl.AnnotationSeq import firrtl.annotations.{Annotation, NoTargetAnnotation} -import firrtl.options.{Phase, PreservesAll, StageOptions, Unserializable} +import firrtl.options.{Phase, PreservesAll, StageOptions, Unserializable, Dependency} import firrtl.options.Viewer.view import freechips.rocketchip.stage.RocketChipOptions import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation} @@ -24,8 +24,8 @@ case class CustomMakefragSnippet(val toMakefrag: String) extends NoTargetAnnotat class GenerateTestSuiteMakefrags extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils { // Our annotations tend not to be serializable, but are not marked as such. - override val prerequisites = Seq(classOf[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], - classOf[chipyard.stage.phases.AddDefaultTests]) + override val prerequisites = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], + Dependency[chipyard.stage.phases.AddDefaultTests]) override def transform(annotations: AnnotationSeq): AnnotationSeq = { val targetDir = view[StageOptions](annotations).targetDir