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Merge branch 'master' into bump_chisel_3.2.x

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Colin Schmidt
2020-02-19 18:05:16 -08:00
parent db0efd38fc 8ca876503c
commit a00771d33a
1 changed files with 2 additions and 1 deletions
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3
macros/src/main/scala/MacroCompiler.scala
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@@ -549,11 +549,12 @@ class MacroCompilerPass(mems: Option[Seq[Macro]],
} }
} }
// Connect mem outputs // Connect mem outputs
val zeroOutputValue: Expression = UIntLiteral(0, IntWidth(mem.src.width))
mem.src.ports foreach { port => mem.src.ports foreach { port =>
port.output match { port.output match {
case Some(PolarizedPort(mem, _)) => outputs get mem match { case Some(PolarizedPort(mem, _)) => outputs get mem match {
case Some(select) => case Some(select) =>
val output = (select foldRight (zero: Expression)) { val output = (select foldRight (zeroOutputValue)) {
case ((cond, tval), fval) => Mux(cond, tval, fval, fval.tpe) } case ((cond, tval), fval) => Mux(cond, tval, fval, fval.tpe) }
stmts += Connect(NoInfo, WRef(mem), output) stmts += Connect(NoInfo, WRef(mem), output)
case None => case None =>