From 8ca876503c71cb6779a956b30bb17078d0f4ef1f Mon Sep 17 00:00:00 2001
From: Albert Magyar <albert.magyar@gmail.com>
Date: Tue, 11 Feb 2020 20:04:22 -0700
Subject: [PATCH] Correctly specify width of default zero output value (#74)

---
 macros/src/main/scala/MacroCompiler.scala | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/macros/src/main/scala/MacroCompiler.scala b/macros/src/main/scala/MacroCompiler.scala
index 09b86c87..652e36e9 100644
--- a/macros/src/main/scala/MacroCompiler.scala
+++ b/macros/src/main/scala/MacroCompiler.scala
@@ -549,11 +549,12 @@ class MacroCompilerPass(mems: Option[Seq[Macro]],
       }
     }
     // Connect mem outputs
+    val zeroOutputValue: Expression = UIntLiteral(0, IntWidth(mem.src.width))
     mem.src.ports foreach { port =>
       port.output match {
         case Some(PolarizedPort(mem, _)) => outputs get mem match {
           case Some(select) =>
-            val output = (select foldRight (zero: Expression)) {
+            val output = (select foldRight (zeroOutputValue)) {
               case ((cond, tval), fval) => Mux(cond, tval, fval, fval.tpe) }
             stmts += Connect(NoInfo, WRef(mem), output)
           case None =>