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update rocketchip

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This commit is contained in:
Howard Mao
2017-07-12 10:44:27 -07:00
parent e2002cb62a
commit 984827db2e
6 changed files with 18 additions and 21 deletions
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2
rocket-chip

Submodule rocket-chip updated: 1f18a37f01...af3976aa67

10
src/main/scala/example/Configs.scala
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@@ -1,10 +1,10 @@
package example package example
import chisel3._ import chisel3._
import config.{Parameters, Config} import freechips.rocketchip.chip.WithoutTLMonitors
import diplomacy.LazyModule import freechips.rocketchip.config.{Parameters, Config}
import coreplex.WithRoccExample import freechips.rocketchip.coreplex.WithRoccExample
import rocketchip.WithoutTLMonitors import freechips.rocketchip.diplomacy.LazyModule
import testchipip._ import testchipip._
class WithExampleTop extends Config((site, here, up) => { class WithExampleTop extends Config((site, here, up) => {
@@ -52,7 +52,7 @@ class WithSimNetwork extends Config((site, here, up) => {
class BaseExampleConfig extends Config( class BaseExampleConfig extends Config(
new WithoutTLMonitors ++ new WithoutTLMonitors ++
new WithSerialAdapter ++ new WithSerialAdapter ++
new rocketchip.DefaultConfig) new freechips.rocketchip.chip.DefaultConfig)
class DefaultExampleConfig extends Config( class DefaultExampleConfig extends Config(
new WithExampleTop ++ new BaseExampleConfig) new WithExampleTop ++ new BaseExampleConfig)

14
src/main/scala/example/PWM.scala
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@@ -2,14 +2,12 @@ package example
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
import config.{Parameters, Field} import freechips.rocketchip.config.{Parameters, Field}
import uncore.tilelink._ import freechips.rocketchip.chip._
import uncore.tilelink2._ import freechips.rocketchip.diplomacy._
import junctions._ import freechips.rocketchip.regmapper.{HasRegMap, RegField}
import diplomacy._ import freechips.rocketchip.tilelink._
import regmapper.{HasRegMap, RegField} import freechips.rocketchip.util.UIntIsOneOf
import rocketchip._
import _root_.util.UIntIsOneOf
case class PWMParams(address: BigInt, beatBytes: Int) case class PWMParams(address: BigInt, beatBytes: Int)

7
src/main/scala/example/TestHarness.scala
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@@ -1,10 +1,9 @@
package example package example
import diplomacy.LazyModule
import rocketchip._
import testchipip._
import chisel3._ import chisel3._
import config.{Field, Parameters} import freechips.rocketchip.diplomacy.LazyModule
import freechips.rocketchip.config.{Field, Parameters}
import testchipip.GeneratorApp
case object BuildTop extends Field[Parameters => ExampleTopModule[ExampleTop]] case object BuildTop extends Field[Parameters => ExampleTopModule[ExampleTop]]

4
src/main/scala/example/Top.scala
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@@ -1,9 +1,9 @@
package example package example
import chisel3._ import chisel3._
import config.Parameters import freechips.rocketchip.config.Parameters
import freechips.rocketchip.chip._
import testchipip._ import testchipip._
import rocketchip._
class ExampleTop(implicit p: Parameters) extends BaseSystem class ExampleTop(implicit p: Parameters) extends BaseSystem
with HasPeripheryMasterAXI4MemPort with HasPeripheryMasterAXI4MemPort

2
testchipip

Submodule testchipip updated: 7b777eb88b...80069b22aa