diff --git a/rocket-chip b/rocket-chip
index 1f18a37f..af3976aa 160000
--- a/rocket-chip
+++ b/rocket-chip
@@ -1 +1 @@
-Subproject commit 1f18a37f01f1034b501a7f4c2edaaffb292d7186
+Subproject commit af3976aa6795f74110e5323c19fc0f5f38f9dbca
diff --git a/src/main/scala/example/Configs.scala b/src/main/scala/example/Configs.scala
index 4b4d915b..75ab6d9e 100644
--- a/src/main/scala/example/Configs.scala
+++ b/src/main/scala/example/Configs.scala
@@ -1,10 +1,10 @@
 package example
 
 import chisel3._
-import config.{Parameters, Config}
-import diplomacy.LazyModule
-import coreplex.WithRoccExample
-import rocketchip.WithoutTLMonitors
+import freechips.rocketchip.chip.WithoutTLMonitors
+import freechips.rocketchip.config.{Parameters, Config}
+import freechips.rocketchip.coreplex.WithRoccExample
+import freechips.rocketchip.diplomacy.LazyModule
 import testchipip._
 
 class WithExampleTop extends Config((site, here, up) => {
@@ -52,7 +52,7 @@ class WithSimNetwork extends Config((site, here, up) => {
 class BaseExampleConfig extends Config(
   new WithoutTLMonitors ++
   new WithSerialAdapter ++
-  new rocketchip.DefaultConfig)
+  new freechips.rocketchip.chip.DefaultConfig)
 
 class DefaultExampleConfig extends Config(
   new WithExampleTop ++ new BaseExampleConfig)
diff --git a/src/main/scala/example/PWM.scala b/src/main/scala/example/PWM.scala
index b9173467..19294acb 100644
--- a/src/main/scala/example/PWM.scala
+++ b/src/main/scala/example/PWM.scala
@@ -2,14 +2,12 @@ package example
 
 import chisel3._
 import chisel3.util._
-import config.{Parameters, Field}
-import uncore.tilelink._
-import uncore.tilelink2._
-import junctions._
-import diplomacy._
-import regmapper.{HasRegMap, RegField}
-import rocketchip._
-import _root_.util.UIntIsOneOf
+import freechips.rocketchip.config.{Parameters, Field}
+import freechips.rocketchip.chip._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.regmapper.{HasRegMap, RegField}
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util.UIntIsOneOf
 
 case class PWMParams(address: BigInt, beatBytes: Int)
 
diff --git a/src/main/scala/example/TestHarness.scala b/src/main/scala/example/TestHarness.scala
index f0d00ab3..c0c0e67e 100644
--- a/src/main/scala/example/TestHarness.scala
+++ b/src/main/scala/example/TestHarness.scala
@@ -1,10 +1,9 @@
 package example
 
-import diplomacy.LazyModule
-import rocketchip._
-import testchipip._
 import chisel3._
-import config.{Field, Parameters}
+import freechips.rocketchip.diplomacy.LazyModule
+import freechips.rocketchip.config.{Field, Parameters}
+import testchipip.GeneratorApp
 
 case object BuildTop extends Field[Parameters => ExampleTopModule[ExampleTop]]
 
diff --git a/src/main/scala/example/Top.scala b/src/main/scala/example/Top.scala
index a5305536..1684d002 100644
--- a/src/main/scala/example/Top.scala
+++ b/src/main/scala/example/Top.scala
@@ -1,9 +1,9 @@
 package example
 
 import chisel3._
-import config.Parameters
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.chip._
 import testchipip._
-import rocketchip._
 
 class ExampleTop(implicit p: Parameters) extends BaseSystem
     with HasPeripheryMasterAXI4MemPort
diff --git a/testchipip b/testchipip
index 7b777eb8..80069b22 160000
--- a/testchipip
+++ b/testchipip
@@ -1 +1 @@
-Subproject commit 7b777eb88bfa8a0433278c0465d29b13028459a1
+Subproject commit 80069b22aa20eaae127f64bd446af13340775c66