make sure mstatus bits are set properly before entering second boot stage

bootrom/bootrom.S

@@ -14,16 +14,7 @@ interrupt_loop:
   addi a2, a2, 4
   lw a3, -4(a2)
   bnez a3, interrupt_loop
-
-boot_core:
-  sll a0, a0, 2 // offset for hart msip
-  add a0, a0, a1
-  sw zero, 0(a0) // clear the interrupt
-  li a0, DRAM_BASE // program reset vector
-  csrw mepc, a0 // return from interrupt to start of user program
-  csrr a0, mhartid // hartid for next level bootloader
-  la a1, _dtb // dtb address for next level bootloader
-  mret
+  j boot_core
 
 .section .text.hang, "ax", @progbits
 .globl _hang
@@ -40,4 +31,16 @@ wfi_loop:
   wfi
   j wfi_loop
 
+boot_core:
+  sll a0, a0, 2 // offset for hart msip
+  add a0, a0, a1
+  sw zero, 0(a0) // clear the interrupt
+  li a0, DRAM_BASE // program reset vector
+  csrw mepc, a0 // return from interrupt to start of user program
+  csrr a0, mhartid // hartid for next level bootloader
+  la a1, _dtb // dtb address for next level bootloader
+  li a2, 0x80 // set mstatus MPIE to 0
+  csrc mstatus, a2
+  mret
+
 _dtb: