47 lines
1.1 KiB
ArmAsm
47 lines
1.1 KiB
ArmAsm
#define DRAM_BASE 0x80000000
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.section .text.start, "ax", @progbits
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.globl _start
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_start:
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li a1, 0x2000000 // base address of clint
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csrr a0, mhartid
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bnez a0, boot_core
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addi a2, a1, 4
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li a3, 1
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interrupt_loop:
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sw a3, 0(a2)
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addi a2, a2, 4
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lw a3, -4(a2)
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bnez a3, interrupt_loop
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j boot_core
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.section .text.hang, "ax", @progbits
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.globl _hang
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_hang:
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// This boot ROM doesn't know about any boot devices, so it just spins,
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// waiting for the serial interface to load the program and interrupt it
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la a0, _start
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csrw mtvec, a0
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li a0, 8 // MIE or MSIP bit
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csrw mie, a0 // set only MSIP in mie CSR
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csrw mideleg, zero // no delegation
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csrs mstatus, a0 // set MIE in mstatus CSR
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wfi_loop:
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wfi
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j wfi_loop
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boot_core:
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sll a0, a0, 2 // offset for hart msip
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add a0, a0, a1
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sw zero, 0(a0) // clear the interrupt
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li a0, DRAM_BASE // program reset vector
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csrw mepc, a0 // return from interrupt to start of user program
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csrr a0, mhartid // hartid for next level bootloader
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la a1, _dtb // dtb address for next level bootloader
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li a2, 0x80 // set mstatus MPIE to 0
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csrc mstatus, a2
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mret
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_dtb:
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