Fixed TinyRocketConfig | Small cleanup to VCU118/Arty configs
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@@ -33,10 +33,7 @@ class WithArtyTweaks extends Config(
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new WithArtyResetHarnessBinder ++
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new WithArtyResetHarnessBinder ++
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new WithDebugResetPassthrough ++
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new WithDebugResetPassthrough ++
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new WithDefaultPeripherals ++
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new WithDefaultPeripherals ++
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new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$
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new freechips.rocketchip.subsystem.WithNBreakpoints(2))
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new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory
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new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++
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new freechips.rocketchip.subsystem.WithIncoherentBusTopology)
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class TinyRocketArtyConfig extends Config(
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class TinyRocketArtyConfig extends Config(
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new WithArtyTweaks ++
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new WithArtyTweaks ++
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@@ -26,7 +26,6 @@ class WithDefaultPeripherals extends Config((site, here, up) => {
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})
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})
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class WithSystemModifications extends Config((site, here, up) => {
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class WithSystemModifications extends Config((site, here, up) => {
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case DebugModuleKey => None // disable debug module
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case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(site(FPGAFrequencyKey).toInt*1000000))
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case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(site(FPGAFrequencyKey).toInt*1000000))
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case DTSTimebase => BigInt(1000000)
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case DTSTimebase => BigInt(1000000)
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case BootROMLocated(x) => up(BootROMLocated(x), site).map { p =>
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case BootROMLocated(x) => up(BootROMLocated(x), site).map { p =>
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@@ -55,7 +54,8 @@ class WithVCU118Tweaks extends Config(
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new WithTLIOPassthrough ++
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new WithTLIOPassthrough ++
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new WithDefaultPeripherals ++
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new WithDefaultPeripherals ++
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new WithTLBackingMemory ++ // use TL backing memory
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new WithTLBackingMemory ++ // use TL backing memory
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new WithSystemModifications ++ // remove debug module, setup busses, use sdboot bootrom, setup ext. mem. size, use new dig. top
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new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size
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new chipyard.config.WithNoDebug ++ // remove debug module
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new freechips.rocketchip.subsystem.WithoutTLMonitors ++
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new freechips.rocketchip.subsystem.WithoutTLMonitors ++
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new freechips.rocketchip.subsystem.WithNMemoryChannels(1))
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new freechips.rocketchip.subsystem.WithNMemoryChannels(1))
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@@ -177,6 +177,10 @@ class WithNoDebug extends Config((site, here, up) => {
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case DebugModuleKey => None
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case DebugModuleKey => None
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})
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})
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class WithTLSerialLocation(masterWhere: TLBusWrapperLocation, slaveWhere: TLBusWrapperLocation) extends Config((site, here, up) => {
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case SerialTLAttachKey => up(SerialTLAttachKey, site).copy(masterWhere = masterWhere, slaveWhere = slaveWhere)
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})
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class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz)
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class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz)
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class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => {
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class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => {
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@@ -11,7 +11,13 @@ class RocketConfig extends Config(
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new chipyard.config.AbstractConfig)
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new chipyard.config.AbstractConfig)
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class TinyRocketConfig extends Config(
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class TinyRocketConfig extends Config(
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new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core
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new chipyard.config.WithTLSerialLocation(
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freechips.rocketchip.subsystem.FBUS,
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freechips.rocketchip.subsystem.PBUS) ++ // attach TL serial adapter to f/p busses
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new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ // use incoherent bus topology
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new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$
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new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory
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new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core
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new chipyard.config.AbstractConfig)
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new chipyard.config.AbstractConfig)
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class HwachaRocketConfig extends Config(
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class HwachaRocketConfig extends Config(
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