From 8f6de22e72c52de67fbaa5f317173f884ea6cd95 Mon Sep 17 00:00:00 2001
From: abejgonzalez <abe.j.gonza@gmail.com>
Date: Mon, 23 Nov 2020 16:30:39 -0800
Subject: [PATCH] Fixed TinyRocketConfig | Small cleanup to VCU118/Arty configs

---
 fpga/src/main/scala/arty/Configs.scala                    | 5 +----
 fpga/src/main/scala/vcu118/Configs.scala                  | 4 ++--
 generators/chipyard/src/main/scala/ConfigFragments.scala  | 4 ++++
 .../chipyard/src/main/scala/config/RocketConfigs.scala    | 8 +++++++-
 4 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala
index 2a78a54c..fa9a47e0 100644
--- a/fpga/src/main/scala/arty/Configs.scala
+++ b/fpga/src/main/scala/arty/Configs.scala
@@ -33,10 +33,7 @@ class WithArtyTweaks extends Config(
   new WithArtyResetHarnessBinder ++
   new WithDebugResetPassthrough ++
   new WithDefaultPeripherals ++
-  new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$
-  new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory
-  new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++
-  new freechips.rocketchip.subsystem.WithIncoherentBusTopology)
+  new freechips.rocketchip.subsystem.WithNBreakpoints(2))
 
 class TinyRocketArtyConfig extends Config(
   new WithArtyTweaks ++
diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala
index 44913ba2..5bd21245 100644
--- a/fpga/src/main/scala/vcu118/Configs.scala
+++ b/fpga/src/main/scala/vcu118/Configs.scala
@@ -26,7 +26,6 @@ class WithDefaultPeripherals extends Config((site, here, up) => {
 })
 
 class WithSystemModifications extends Config((site, here, up) => {
-  case DebugModuleKey => None // disable debug module
   case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(site(FPGAFrequencyKey).toInt*1000000))
   case DTSTimebase => BigInt(1000000)
   case BootROMLocated(x) => up(BootROMLocated(x), site).map { p =>
@@ -55,7 +54,8 @@ class WithVCU118Tweaks extends Config(
   new WithTLIOPassthrough ++
   new WithDefaultPeripherals ++
   new WithTLBackingMemory ++ // use TL backing memory
-  new WithSystemModifications ++ // remove debug module, setup busses, use sdboot bootrom, setup ext. mem. size, use new dig. top
+  new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size
+  new chipyard.config.WithNoDebug ++ // remove debug module
   new freechips.rocketchip.subsystem.WithoutTLMonitors ++
   new freechips.rocketchip.subsystem.WithNMemoryChannels(1))
 
diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala
index 68c41724..4bc0b9a2 100644
--- a/generators/chipyard/src/main/scala/ConfigFragments.scala
+++ b/generators/chipyard/src/main/scala/ConfigFragments.scala
@@ -177,6 +177,10 @@ class WithNoDebug extends Config((site, here, up) => {
   case DebugModuleKey => None
 })
 
+class WithTLSerialLocation(masterWhere: TLBusWrapperLocation, slaveWhere: TLBusWrapperLocation) extends Config((site, here, up) => {
+  case SerialTLAttachKey => up(SerialTLAttachKey, site).copy(masterWhere = masterWhere, slaveWhere = slaveWhere)
+})
+
 class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz)
 
 class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => {
diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
index 626700a5..40511eef 100644
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -11,7 +11,13 @@ class RocketConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 class TinyRocketConfig extends Config(
-  new freechips.rocketchip.subsystem.With1TinyCore ++            // single tiny rocket-core
+  new chipyard.config.WithTLSerialLocation(
+    freechips.rocketchip.subsystem.FBUS,
+    freechips.rocketchip.subsystem.PBUS) ++                       // attach TL serial adapter to f/p busses
+  new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ // use incoherent bus topology
+  new freechips.rocketchip.subsystem.WithNBanks(0) ++             // remove L2$
+  new freechips.rocketchip.subsystem.WithNoMemPort ++             // remove backing memory
+  new freechips.rocketchip.subsystem.With1TinyCore ++             // single tiny rocket-core
   new chipyard.config.AbstractConfig)
 
 class HwachaRocketConfig extends Config(