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Fix UARTPort freqMHz

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This commit is contained in:
Jerry Zhao
2023-10-07 00:27:15 -07:00
parent 5145f4f243
commit 8d11dde7cb
1 changed files with 2 additions and 2 deletions
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4
generators/chipyard/src/main/scala/iobinders/IOBinders.scala
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@@ -208,8 +208,8 @@ class WithUARTIOCells extends OverrideIOBinder({
val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", system.p(IOCellKey), abstractResetAsAsync = true) val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", system.p(IOCellKey), abstractResetAsAsync = true)
val where = PBUS // TODO fix val where = PBUS // TODO fix
val bus = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where) val bus = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
val freqMHz = bus.dtsFrequency.get.toInt / 1000000 val freqMHz = bus.dtsFrequency.get / 1000000
(UARTPort(port, i, freqMHz), ios) (UARTPort(port, i, freqMHz.toInt), ios)
}).unzip }).unzip
(ports, cells2d.flatten) (ports, cells2d.flatten)
} }