diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
index 7cbce516..773f3d39 100644
--- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
@@ -208,8 +208,8 @@ class WithUARTIOCells extends OverrideIOBinder({
       val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", system.p(IOCellKey), abstractResetAsAsync = true)
       val where = PBUS // TODO fix
       val bus = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
-      val freqMHz = bus.dtsFrequency.get.toInt / 1000000
-      (UARTPort(port, i, freqMHz), ios)
+      val freqMHz = bus.dtsFrequency.get / 1000000
+      (UARTPort(port, i, freqMHz.toInt), ios)
     }).unzip
     (ports, cells2d.flatten)
   }