From 8d11dde7cb180d7ac776c71b158e4ce5da555711 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Sat, 7 Oct 2023 00:27:15 -0700
Subject: [PATCH] Fix UARTPort freqMHz

---
 generators/chipyard/src/main/scala/iobinders/IOBinders.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
index 7cbce516..773f3d39 100644
--- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
@@ -208,8 +208,8 @@ class WithUARTIOCells extends OverrideIOBinder({
       val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", system.p(IOCellKey), abstractResetAsAsync = true)
       val where = PBUS // TODO fix
       val bus = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
-      val freqMHz = bus.dtsFrequency.get.toInt / 1000000
-      (UARTPort(port, i, freqMHz), ios)
+      val freqMHz = bus.dtsFrequency.get / 1000000
+      (UARTPort(port, i, freqMHz.toInt), ios)
     }).unzip
     (ports, cells2d.flatten)
   }